Semiconductor chip package

Details Semiconductor chip package Semiconductor chip package

2006-12-19

2006-12-19

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With means to prevent explosion of package

C257SE23145, C257SE23194

Reexamination Certificate

active

07151308

ABSTRACT:
A semiconductor chip package includes an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The peripheral substrate is separated from the central substrate thereby decreasing the stresses caused by CTE mismatch of the semiconductor chip package. Furthermore, both the central substrate and the peripheral substrate are mechanically and electrically connected to the interconnection substrate such that the semiconductor chip is electrically connected to the peripheral substrate through the central substrate and the interconnection substrate.

REFERENCES:
patent: 6710457 (2004-03-01), Silverbrook
patent: 6720647 (2004-04-01), Fukuizumi
patent: 2003/0071353 (2003-04-01), Noguchi
patent: 2003/0146508 (2003-08-01), Chen et al.
patent: 2005/0078434 (2005-04-01), Ho
patent: 2000100866 (2000-04-01), None

Affiliated with

Also associated with

Rating

Semiconductor chip package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor chip package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor chip package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3720372