Semiconductor chip having a bonding window smaller than a wire b

Details Semiconductor chip having a bonding window smaller than a wire b Semiconductor chip having a bonding window smaller than a wire b

1996-12-20

1999-04-27

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257781, 257784, 257751, 257737, H01L 21316, H01L 2160, H01L 21321

Patent

active

058982264

ABSTRACT:
A semiconductor chip is provided comprising a semiconductor substrate having determined circuit elements on it, a surface-smoothing layer deposited on the substrate, a bonding pad formed on the smoothing layer and connected electrically to the circuit elements, a passivation layer formed on the surface-smoothing layer, the passivation layer having a window for exposing a part of the bonding pad, and a second metal layer having a same height as the passivation layer and occupying peripheral parts of the window to form a reduced bonding windows for the bonding pad.

REFERENCES:
patent: 4733289 (1988-03-01), Tsurumaru
patent: 5430329 (1995-07-01), Harada et al.
patent: 5665996 (1997-09-01), Williams et al.

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