Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2000-09-29
2002-02-19
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S783000, C438S118000
Reexamination Certificate
active
06348741
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor apparatus having a chip size package of the type used for a high density assembly module and a multi-chip module.
Recently, in association with the trend toward miniaturization and high performance of electronic devices, high density packing, high densification, and an increase in the speed of processing are also required for the semiconductor devices used therein. In correspondence with this objective, as a semiconductor apparatus mounting method, packages have been developed from the pin insertion type to the surface mounting type in order to increase the mounting density, and from a DIP (dual inline package) to a QFP (quad flat package) or a PGA (pin grid array) so as to correspond to the multi-pin type.
However, in the QFP type, the connection lead wires from the mounting substrate are centralized only in the peripheral part of the package, and the lead wires themselves are thin and deformable, so that, as the number of pins increases, the mounting has become more difficult. In the PGA type, the terminals to be connected to the mounting substrate are long and thin and centralized extremely, so that speeding up of the processing is difficult on an electric characteristic basis, and, since it is of a pin insertion type, surface mounting is not available and the type is disadvantageous in high density assembly.
Recently, to solve these problems and realize a semiconductor apparatus which is capable of high speed, a BGA (ball grid array) package has been developed which has a stress cushioning layer between a semiconductor chip and a substrate with a wiring circuit formed thereon, and a bump electrode is provided as an external terminal on the mounting substrate surface side of the substrate (U.S. Pat. No. 5,148,265). In a package having this structure, the terminals to be connected to the mounting substrate are ball-shaped solder, so that the lead wires are free of deformation, unlike the QFP type, and the terminals are scattered over all of the mounting surface. Hence, the pitch between the terminals can be made longer and the surface mounting is easy. The bump electrode, which is an external terminal, is shorter than that of the PGA type, so that the inductance component is small and the signal speed is fast. Hence, the structure can provide for high speed operation.
Recently, in association with wide spread use of portable information terminals, miniaturization and high density assembly of a semiconductor apparatus are required. Therefore, recently, a CSP (chip scale package) having a package size almost equal to the size of the chip has been developed. In “Nikkei Microdevice” (p. 38 to p. 64) issued by Nikkei BP, Ltd. (February 1998), various types of CSPs are disclosed. These CSPs are manufactured in such a way that semiconductor chips cut into pieces are adhered to a polyimide or ceramics substrate with a wiring layer formed thereon, and then the wiring layer and semiconductor chips are electrically connected by wire bonding, single point bonding, gang bonding, or bump bonding, and the connections are sealed with resin, and finally an external terminal, such as a solder bump is formed.
Japanese Patent Application Laid-open 9-232256 and Japanese Patent Application Laid-Open 10-27827 disclose methods for mass-producing CSPs. The methods form a bump on a semiconductor wafer, electrically connect a wiring substrate via the bump, then seal the connections with resin, form an external electrode on the wiring substrate, and finally cut it into pieces, in the manufacture of a semiconductor apparatus.
“Nikkei Microdevice” (p. 164 to p. 167) issued by Nikkei BP, Ltd. (April 1998) discloses another method for mass-producing CSPs. The method forms a bump on a semiconductor wafer by plating, seals the part other than the bump with resin, forms an external electrode in the bump part, and then cuts it into pieces, in the manufactures of a semiconductor apparatus.
Japanese Patent Application Laid-open 10-92865 discloses a semiconductor apparatus of a type having a resin layer for cushioning the stress between an external electrode and semiconductor chips, in which chips are processed in units of wafers in a batch and then cut into pieces.
SUMMARY OF THE INVENTION
In the aforementioned semiconductor apparatuses of the type wherein, after resin layers and external electrodes are formed, in a batch, in units of semiconductor wafers and the wafers are then cut into pieces, the interfaces of the layers are always exposed on the end face of the package. Therefore, due to the thermal stress caused by sudden temperature changes at the time of mounting the package and the mechanical stress at the time of the dicing of the chips into pieces, the stress is centralized on the interfaces between the chips and the resin layers which are exposed at the end of the package, and peeling is generated from there, so that the package is damaged. As a result, the reliability of the semiconductor apparatus is reduced, and the manufacturing yield rate also is reduced.
The present invention, with the foregoing in view, provides a semiconductor apparatus of high reliability and a semiconductor apparatus manufacturing method having a high manufacturing yield rate for preventing stress concentration on interfaces and suppressing peeling-off between chips and resin layers when thermal stress and mechanical stress are applied to a package.
The aforementioned problems can be solved by the features indicated below. The following is a summary of the features of the present invention.
(1) In a semiconductor apparatus having, on the surface of a semiconductor chip having a circuit and an electrode formed thereon, a stress cushioning layer on a part other than where the electrode is formed, a wiring layer connected to the electrode on the stress cushioning layer, an external protection film on the wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window, wherein the stress cushioning layer, wiring layer, conductor, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.
(2) In a semiconductor apparatus having, on the surface of a semiconductor chip having a circuit and an electrode formed thereon, a chip protection film on a part other than where the electrode is formed, a first wiring layer and a stress cushioning layer connected to the electrode on the chip protection film, a second wiring layer connected to the first wiring layer on the stress cushioning layer, an external protection film on the second wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window, wherein the chip protection film, stress cushioning layer, wiring layer, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.
(3) A semiconductor apparatus manufacturing method having 1. a step of forming a stress cushioning layer on a circuit forming surface of a semiconductor wafer on which a plurality of semiconductor elements are formed, 2. a step of forming an opening for exposing the chip electrode on the stress cushioning layer on an electrode of the semiconductor wafer, 3. a step of forming a slit in the stress cushioning layer on a scribe line for cutting the semiconductor wafer, 4. a step of forming a wiring layer connected to the electrode of the semiconductor chip on the stress cushioning layer via the opening, 5. a step of forming an external protection film having a window for connecting an external electrode on the stress cushioning layer and wiring layer except for the scribe line, 6. a step of forming an external electrode, and 7. a step of cutting the semiconductor wafer in a min
Anjo Ichiro
Miwa Takao
Nagai Akira
Nishimura Asao
Ogino Masahiko
LandOfFree
Semiconductor apparatus and a manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor apparatus and a manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor apparatus and a manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2945019