Self-testing of DRAMs for multiple faults

Details Self-testing of DRAMs for multiple faults Self-testing of DRAMs for multiple faults

1998-08-13

2001-12-11

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000

Reexamination Certificate

active

06330696

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a method of self-testing memory units and, more particularly, to a method of self-testing dynamic random access memories (DRAMs).
BACKGROUND OF THE INVENTION
In U.S. Pat. No. 5,513,318 assigned to the assignee of the present invention, a technique is disclosed for accomplishing the “built-in” self-testing (BIST) of first-in, first-out (FIFO) memory units employing ring counter accessing of static random access memory units (SRAM)s. Sequences of operations are performed on the memory unit under test to detect faults associated with the read-out of spurious data in the presence and absence of real data having been stored in the memory, the ability to accept read and write commands, the resetting of the read and write access registers simultaneously and independently, etc., including alteration of various flag signals normally set or unset to indicate proper memory operation. While the arrangement described in the above-mentioned patent operates satisfactorily, it would be advantageous to achieve a self-testing ability for memory units other than FIFO memories and, in particular, to dynamic random access memories (DRAM)s.
A DRAM differs from an SRAM in the technology of the memory cell employed for the storage of binary information. Basically, the SRAM uses a flip-flop in each memory cell which remains indefinitely in the state to which it has been set. The DRAM memory cell employs a capacitor to store a charge whose value must periodically be refreshed because the charge tends to leak-off with time. Typically, an SRAM requires approximately 6 transistors per memory cell while a DRAM memory will employ only two transistors per memory cell, one of which is employed for accessing and the other of which stores the charge. Often “two-rail” logic is used so that a cell C
i,j
is provided to store a bit value (data bit b) and a conjugate cell
C
i,j
is provided to store the opposite bit value b. Because fewer transistors are required in the DRAM memory these memories tend to be used where high information storage density is required while SRAM memory is used where fast access is required.
Because the technology of the DRAM capacitor memory cell differs from that of the SRAM, its failures occur in ways that are entirely different from the way that an SRAM may fail. Because of these differences, some of the testing techniques applicable to SRAMs will not operate satisfactorily with DRAMs. Accordingly, it would be desirable to be able to provide a self-test routine which took into account the different ways that failure can occur in a DRAM so that appropriate remedial measures could be taken.
SUMMARY OF THE INVENTION
The foregoing and other objects are achieved in an illustrative embodiment of the present invention in which a DRAM memory unit is tested for a series of cell faults similar to those occurring in SRAMS such as: the stuck-at fault (SAF), the stuck-open fault (SOF), the transition fault (TF), the multiple address fault (MAF) (arising from static or dynamic coupling, as well as faults in the address decoder. However, to detect such faults in a DRAM it is necessary first to address each location of the DRAM in a prescribed order, writing a predetermined pattern in the location, reading the location, repeating the procedure using a complementary pattern and then repeating both procedures while re-addressing the memory locations in the opposite order.
The DRAM is also tested for a series of faults unlike those that may occur in SRAMs, including storage capacitor leakage, subthreshold leakage or junction leakage causing a defective cell in one portion of the memory to affect values stored in another portion. To test for these faults, a predetermined pattern is written throughout the DRAM memory, a time sufficient for a defective storage element to lose its charge is allowed to elapse, and then locations in a first portion of the memory are either frozen or sequentially addressed to create a disturbance while the locations in a second portion of the memory are read to verify whether changes in the stored pattern have occurred. To check for subthreshold leakage the locations in the first portion are frozen while, to check for storage capacitor leakage or junction leakage, the locations in the first portion are sequentially and repetitively written with a predetermined pattern, following which the locations in the second portion of the memory are read to verify whether the stored values have been changed by the previous step. To check for storage capacitor leakage and junction leakage, the pattern written into memory is a “checkerboard” of alternating “1” and “0” values as well as the complementary checkerboard pattern. Finally, the test is repeated interchanging the first and second portions of memory.


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El-Kareh et al.; “The evolution of DRAM cell Technology”, Solid State Technology, May 1997, pp. 89-101.

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