4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Memory testing

David Lepejian

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Method for selecting an optimal level of redundancy in the...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Self-testing of DRAMs for multiple faults

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Profile ID: LFUS-PAI-P-2142682

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