Self-planarizing DRAM chip avoids edge flaking

Details Self-planarizing DRAM chip avoids edge flaking Self-planarizing DRAM chip avoids edge flaking

1999-06-24

2000-10-10

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438243, 438396, 438585, 438437, 438190, H01L 218242

Patent

active

061301264

ABSTRACT:
The dummy oxide used to form DRAM capacitor cells is left in place over the peripheral transistors, reducing the height difference between the DRAM array and the peripheral circuitry and protecting against edge effects.

REFERENCES:
patent: 5286674 (1994-02-01), Roth et al.
patent: 5504026 (1996-04-01), Kung
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5770499 (1998-06-01), Kwok et al.
patent: 5807775 (1999-09-01), Tseng
patent: 5880018 (1999-05-01), Boeck et al.
patent: 5956587 (1999-09-01), Chen et al.
patent: 5989952 (1999-11-01), Jen et al.
patent: 5993742 (1999-08-01), Wu
patent: 5998260 (1999-12-01), Lin
patent: 5998285 (1999-12-01), Chou

Affiliated with

Also associated with

Rating

Self-planarizing DRAM chip avoids edge flaking does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-planarizing DRAM chip avoids edge flaking, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-planarizing DRAM chip avoids edge flaking will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2255849