Self-aligned silicide (salicide) process for strained...

Details Self-aligned silicide (salicide) process for strained... Self-aligned silicide (salicide) process for strained...

2000-11-15

2003-01-07

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S683000, C438S655000, C438S656000, C438S664000

Reexamination Certificate

active

06503833

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a strained Si MOSFET, and to a method of forming a low resistivity contact to a strained Si MOSFET.
2. Description of the Related Art
Silicon metal oxide semiconductor field effect transistor (MOSFET) scaling requires the continuous reduction of the gate length, the gate dielectric thickness, and higher substrate doping. These requirements contribute to an increased vertical field in the channel, which lowers the channel inversion layer mobility and current drive, as described in K. Rim et al., “Transconductance Enhancement in Deep Submicron Strained-Si N-MOSFET ”, IEDM 1998 Tech. Digest, p. 707, 1998.
The channel mobility of both n-MOSFETs and p-MOSFETs is enhanced if the channel is made of “strained silicon”. The strained silicon channel is obtained by growing a thin pseudomorphic Si layer (e.g., on the order of 15 nm to 20 nm thick) on a relaxed relatively thick Si(1−x)Ge(x), where x is typically 0.2 to 0.3, as described in the above-mentioned Rim et al. and J. Welser et al., IEDM 1994 Tech. Digest, p. 373, 1994.
For purposes of the present invention, “strained-Silicon” means that the silicon film is stretched to accommodate the underlay film lattice constant. For example, if the underlay film has a lattice constant which is larger than that of silicon, the silicon film would be tensely strained. Such straining is performed by forming a relatively thin silicon layer on a substrate, with the silicon layer having a different lattice constant from that of the substrate. However, the upper layer attempts to maintain a same lattice constant as the substrate, and thus is “strained” while attempting to make such an accommodation.
In contrast, “relaxed” in the context of the present application means that the upper layer is formed to be indifferent to the lattice constant of the substrate. Typically, in such a case, the upper layer is relatively thick and thus does not attempt to match the lattices of the substrate.
In practice, the straining of the thin silicon film is achieved by forming the film over a thick Si
(1−x)
Ge
(x)
grown on a Si substrate. The SiGe film is made thick enough (typically more than a micron thick for x=0.3) so that the film relaxes to its bulk lattice constant. Given that the thick SiGe layer is relaxed then for the purpose of forming a strained thin Si film on top of it, it may be viewed as a substrate with a different lattice constant than that of silicon.
The enhancement in mobility was found to be as large as 75% for n-MOSFET devices, as described in Rim et al. and 80% for p-MOSFET devices with x=0.2, as described in Rim et al., “Enhanced Hole Mobility in Surface-Channel Strained-Si p-MOSFET”, IEDM 1995 Tech. Digest, p. 517, 1995. The typical thickness of the strained Si film is approximately 13 nm. An attempt to grow a substantially thicker film tends to cause the layer to relax. It is noted that the thickness of the strained silicon layer will depend on the composition of the underlying buffer layer. Thus, assuming SiGe was used for the buffer layer, using a composition having 40% Germanium would result in a thinner upper silicon layer, whereas using a composition having 30% Germanium would result in a thicker upper silicon layer.
High speed devices require the use of silicide for the source and drain to reduce the parasitic series resistance. However, applying the conventional self-aligned silicide (salicide) process to the strained-Si MOSFET is not straightforward due to several issues and consequently has some drawbacks.
For example, the strained Si film is too thin to accommodate the conventional silicide. For example, if cobalt (Co) is used to make the silicide, then the Si film must be thicker than about 25 nm to accommodate the silicide (CoSi
2
). However, the pseudomorphic Si layer cannot be made thicker than approximately 15 nm (e.g., a critical thickness, which is the maximum thickness which can be grown for the strained layer until it begins to relax; as mentioned above, the critical thickness depends upon the composition of the substrate such as the percentage of germanium, etc. ) or otherwise it relaxes, as mentioned above.
Secondly, since the strained Si film is not thick enough to supply enough Si to form the silicide, the silicide would have to consume some of the underlying SiGe buffer. However, the formation temperature of the silicide in SiGe is higher than in Si, as shown in FIG.
7
.
For example, the lowest formation temperature of CoSi
2
in a single crystal Si
0.7
,Ge
0.3
is about 825° C., as compared with 625 ° C. in pure Si. The higher formation temperature has serious implications such as dopant diffusion in the source and drain, and relaxation of the pseudomorphic strained Si film.
The conventional approach to the above-mentioned problem is to make the silicon thicker in the source and drain regions prior to applying the salicide process. The addition of silicon must be selective, and must be limited only to the source and drain regions (and then to the gate) or otherwise bridging will occur.
On the other hand, if the continuous film of silicon is deposited, the gate and the drain (and source) become connected when the silicide is formed. Thus, to avoid shorting of the gate to the source and drain, a selective deposition must be used. Selective epitaxy is usually the preferred method to add silicon only to the source, drain and gate regions. The silicon epitaxially grows only where a silicon seed exists. Thus, silicon will be added to the gate, source and drain regions which have a silicon (or poly-Si) surface, but no deposition occurs on dielectric surfaces such as the device source/drain spacers.
Unfortunately, the use of selective epitaxy has serious drawbacks. For example, the epitaxial growth must be truly selective. That is, the selectivity of the growth depends on various variables including the growth temperature, the silicon source, and the dielectric material. Usually, a higher growth temperature yields a more selective growth with less deposition on non-silicon surfaces. The requirement for a high growth temperature may exceed the thermal budget allowed by the conventional salicide process. The best known silicon source for selective epitaxy is SiCl
4
. Unfortunately, this source requires a high growth temperature, typically 900° C. to 1200° C. However, applying such a high temperature is not possible, since it would lead to the relaxation of the strained Si film, and to dopant diffusion. Silane (SiH
4
) permits low growth temperatures down to 650° C. Yet, this silicon source is not very selective.
Another problem is process robustness. That is, Si epitaxy is very sensitive to surface preparation and cleaning. Different surface treatments could lead to different defects in the film. Oxide residuals (even an atomic mono layer) could prevent the epitaxial growth.
A third problem is the growth rate dependency on feature size. That is, in chemical vapor deposition (CVD)-type epitaxy, the growth rate may be dependent on the topography, the dimensions of the growth area, and the ratio between the growth to nongrowth areas. This may lead to a growth of different film thicknesses in devices that are embedded in different circuit layouts.
A fourth problem is the relaxation of the Si film in the source/drain region. That is, the thickening of the strained Si film in the source/drain region by epitaxy leads to a strain relaxation of the film. The relaxation typically is achieved by defects that may extend from the source/drain regions into the channel region.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional methods and structures, an object of the present invention is to provide a new self-aligned (salicide) method which is applicable to strained Si MOSFET on, for example, SiGe (Note: for purposes of the present invention, SiGe will be assumed for the buffer layer, but of course other materials can be used as would be known by one of ordinary

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