Self-aligned silicide process

Details Self-aligned silicide process Self-aligned silicide process

1999-11-30

2001-09-11

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S141000, C438S299000, C438S648000, C438S649000, C438S663000, C438S680000, C438S681000, C438S682000, C438S683000

Reexamination Certificate

active

06287967

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a self-aligned silicide (salicide) process.
2. Description of the Related Art
At a deep sub-micron level of semiconductor fabrication technologies, line width, contact area, and junction depth are greatly reduced. In order to effectively enhance device performance, reduce device resistance, and reduce device resistance-capacitance (RC) delay, silicide has gradually taken the place of polysilicon in the formation of conductive parts, such as a gate or interconnects. The formation of a silicide layer has a self-aligned characteristic. Since silicide is formed by a reaction, the usual photolithography process is not necessary. This fabrication process to form a silicide is therefore called a self-aligned silicide (salicide) process. The silicide layer formed through the salicide process is usually called a salicide layer.
A silicide layer, usually, is formed by triggering a reaction between a metallic material and silicon of a substrate through a rapid thermal annealing. After reaction, a silicide material is therefore formed on a silicon interface of the substrate. The silicide material usually includes titanium silicide, tungsten silicide, cobalt silicide, nickel silicide, molybdenum silicide, or platinum silicide, in which titanium silicide is the most widely used because its conductivity is relative higher and it can be easily controlled in fabrication.
Salicide process forms silicide material on a gate electrode and on source/drain regions. The silicide material easily diffuses through source/drain regions to a substrate while forming the silicide material on the source/drain regions. It causes a junction leakage. The effect can be resolved by decreasing a thickness of the silicide material over the source/drain regions. However, thickness of the silicide material on the gate electrode decreasing does increase sheet resistance of the gate electrode.
Furthermore, titanium silicide is usually used for salicide process. Titanium silicide comprises C
49
phase and C
54
phase. The C
49
phase titanium silicide has a higher resistance than the C
54
phase titanium silicide. The C
49
phase titanium silicide can grow at a lower temperature than the C
54
phase titanium silicide. In general, a rapid thermal annealing process can be used to transform the high-resistance, C
49
phase titanium silicide into low-resistance, C
54
phase titanium silicide. However, as the line width of VLSI circuit drops to 0.25 &mgr;m or lower, a higher temperature is required to grow the C
54
phase titanium silicide due to what is known as the narrow size effect. The narrow size effect is a relationship showing the effect of line width on the phase transformation temperature of titanium silicide. The smaller the line width of the integrated circuit is, the higher the phase transformation temperature for transforming high-resistance, C
49
phase titanium silicide into low-resistance, C
54
phase titanium silicide. If a higher temperature is used in a RTP process so that more C
54
phase titanium silicide is formed, the properties of the resultant titanium silicide layer are highly unstable, such as formation of titanium silicide on a side-wall of the gate electrode due to a lateral growth effect. The lateral growth effect may cause a bridge to form between the gate electrode and the source/drain regions.
A conventional salicide method forming cobalt silicide is provided for resolving the narrow size effect. Cobalt atoms can diffuse into polysilicon and react with the polysilicon without the narrow size effect. However, cobalt reacting with silicon at the source/drain regions causes junction leakage.
SUMMARY OF THE INVENTION
The invention provides a self-aligned silicide process. A substrate at least comprising a transistor thereon is provided. The transistor comprises a gate on the substrate, a spacer on the sidewall of the gate, and source/drain region within the substrate beside the gate. A thin metal layer is formed over the substrate by CVD or PVD. A first rapid thermal process is performed to make the metal layer react with polysilicon of the gate and of the source/drain regions to form a first metal silicide layer. The metal layer, which does not react with polysilicon, is removed. A selective raised salicide process is performed to form a second metal silicide layer on the first metal silicide layer using the first metal silicide layer as a nucleation layer. A second rapid thermal process is performed to transfer the first metal silicide layer and the second metal silicide layer from a high-resistance C
49
phase to a low-resistance C
54
phase.
The metal layer is thin so that light polysilicon of the gate and of the source/drain regions is consumed while forming the first metal silicide layer. Furthermore, the second metal silicide layer is selectively formed on the first metal silicide layer and does not form on other materials, such as silicon oxide or silicon nitride. Thus, the position where the second metal silicide layer forms is easily controlled. Junction leakage between the source/drain regions and the substrate can be prevented because light polysilicon of the gate and of the source/drain region is consumed. The thickness of the second metal silicide layer can be increased using the method of the invention rather than using a conventional method. Sheet resistance of the gate can thus be decreased.


REFERENCES:
patent: 5834356 (1998-10-01), Bothra et al.
patent: 5841173 (1998-10-01), Yamashita

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