Self-aligned contact formation for semiconductor devices

Details Self-aligned contact formation for semiconductor devices Self-aligned contact formation for semiconductor devices

2000-02-29

2001-03-27

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S633000, C438S637000, C438S737000

Reexamination Certificate

active

06207571

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to contact formation on an integrated circuit, and more specifically to forming contacts on an integrated circuit to enhance fabrication yield.
BACKGROUND OF THE INVENTION
Integrated circuits, such as dynamic random access memories (DRAMs), are fabricated with devices that have microscopic features that can only be manufactured with processing steps that require careful alignment of equipment used to build the devices. The manufacturing costs of integrated circuits are expensive because (1) the processing steps must be accomplished with costly and sophisticated equipment, and experienced operators, and (2) such steps are not always successful. For example, if the processing equipment, such as a mask, is inadvertently misaligned, then the DRAM may be fabricated incorrectly and fail. As a result, processing yields decrease and production costs increase. Therefore, to reduce manufacturing costs, a DRAM fabrication process that has enhanced process tolerances is desirable. Such a process would permit successful fabrication of DRAMs, despite minor misalignments.
U.S. Pat. No. 5,439,846 to Nguyen et al. (hereinafter the Nguyen Patent), which is herein incorporated by reference, discloses a method of fabricating transistor contacts in DRAMs. The Nguyen Patent teaches consecutively forming silicon nitride, tungsten silicide, polysilicon, gate oxide and a field oxide on a silicon substrate to partially construct a transistor. Subsequently, a nitride etch is performed. Thus, a portion of the silicon nitride, defined by a masking process, is removed to expose the tungsten silicide. As a result, a contact can be later deposited on and connected to the exposed gate contact opening of the transistor.
Next, the Nguyen Patent teaches performing a gate etch to define gate stacks. Thus, portions of silicon nitride, tungsten silicide, polysilicon and gate oxide are removed from the substrate. However, if the nitride and gate etches are misaligned, for example due to mask misalignment, then field oxide may be inadvertently removed, or a sliver of silicon nitride may be formed on the gate contact. If field oxide is inadvertently removed, then the contact could short the gate stack to the silicon substrate. Hence, the transistor gate and active regions may be coupled, disabling the transistor. Alternatively, if the silicon nitride sliver is formed, then it may be more difficult to successfully complete subsequently performed processing steps used to form the contact on the gate contact opening. Therefore, it is desirable to fabricate DRAMs with a process that is more tolerant of misalignments between the nitride and gate etches.
Additionally, the topography of the DRAM is no longer flat after the nitride etch has been performed with the method of the Nguyen Patent. As a result, the lithography step used to define the gate stacks with the process of the Nguyen Patent must be performed with equipment having a relatively large field of depth, which may be more costly. Therefore, there is a need for a DRAM process that is tolerant of misalignments, and does not require lithography equipment with a relatively large field of depth.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. Spacers are formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film.
In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and is not susceptible to over-etched field oxide or silicon nitride slivers.
In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth.
In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact is not inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.
Because it is more tolerant of misalignment, the present invention enhances the yield of current DRAM designs. Also, the present invention permits higher device density in future DRAM designs. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.


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