Self-aligned contact formation for semiconductor devices

Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438737, 438743, H01L 2100

Patent

active

060806729

ABSTRACT:
In accordance with the present invention, there is provided a method for fabricating a contact on an integrated circuit, such as a DRAM. The method includes the following steps. A gate stack is formed on the integrated circuit. A spacer is formed on sidewalls of the gate stack. An insulating film is formed on the integrated circuit. The insulating film is planarized. Finally, a gate contact opening is formed through the planarized insulating film. In one embodiment, the gate contact opening is formed by removing the insulator, spacer and insulating film by etching. In this embodiment, the insulator, spacer and insulating film are etched at substantially similar rates. As a result, the integrated circuit is tolerant of mask misalignments, and does not over-etch field oxide or create silicon nitride slivers. In another embodiment, the planarizing step is performed with chemical mechanical planarization to form a substantially flat topography on the surface of the integrated circuit. Thus, the present invention does not require lithography equipment with a relatively large field of depth. In yet a third embodiment, the method may comprise additional steps, including forming additional dielectric on the integrated circuit. Then, gate and bitline contact openings are formed through the additional dielectric. Finally, gate and bitline contacts are formed in self-alignment to the gate stacks. This embodiment may be implemented by forming the gate and bitline contact openings with an etch that removes the additional dielectric, but does not substantially remove the spacer. As a result, the bitline contact cannot be inadvertently connected to a gate stack that functions as a wordline. This connection might disable the integrated circuit.

REFERENCES:
patent: 4354896 (1982-10-01), Hunter et al.
patent: 4656732 (1987-04-01), Teng et al.
patent: 4792534 (1988-12-01), Tsuji et al.
patent: 4801350 (1989-01-01), Mattox et al.
patent: 4912061 (1990-03-01), Nasr
patent: 4962414 (1990-10-01), Liou et al.
patent: 5117273 (1992-05-01), Stark et al.
patent: 5175127 (1992-12-01), Manning
patent: 5206187 (1993-04-01), Doan et al.
patent: 5229326 (1993-07-01), Dennison et al.
patent: 5252517 (1993-10-01), Blalock et al.
patent: 5292677 (1994-03-01), Dennison
patent: 5300807 (1994-04-01), Nelson
patent: 5362666 (1994-11-01), Dennison
patent: 5411909 (1995-05-01), Manning et al.
patent: 5439846 (1995-08-01), Nguyen et al.
patent: 5488011 (1996-01-01), Figura et al.
patent: 5498570 (1996-03-01), Becker
patent: 5605864 (1997-02-01), Prall
patent: 5688720 (1997-11-01), Hayashi
patent: 5724282 (1998-03-01), Loughmiller, D. R., et al.
patent: 5863837 (1999-01-01), Sudo
patent: 5872740 (1999-02-01), Loughmiller, D.R., et al.
patent: 5914279 (1999-06-01), Yang et al.
"Method to Produce Sizesin Openings in Photo Images Smaller than Lithographic Minimum Size", IBM Technical Disclosure Bulletin, 29, 1328, (Aug. 1986).
"Methods of Forming Small Contact Holes", IBM Technical Disclosure Bulletin, 30, 252, (Jan. 1988).
Fukase, T., et al., "A Margin-Free Contact Process Using An Al.sub.2 O.sub.3 Etch-Stop Layer for High Density Devices", International Electron Devices Meeting: Technical Digest, 837-840, (1992).
Lau, C., et al., "A Super Self-Aligned Source/Drain MOSFET", International Electron Devices Meeting: Technical Digest, 358-361, (1987).
Singer, P., "A New Technology for Oxide Contact and Via Etch", Semiconductor International, 36, (Aug. 1993).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Self-aligned contact formation for semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned contact formation for semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned contact formation for semiconductor devices will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1784591

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.