Selective landing pad fabricating methods for integrated circuit

Details Selective landing pad fabricating methods for integrated circuit Selective landing pad fabricating methods for integrated circuit

1996-10-15

1999-05-25

Brown, Peter Toby

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438201, 438203, 438279, 438287, H01L 21336

Patent

active

059077794

ABSTRACT:
An integrated circuit is fabricated by forming first source and drain regions and contact regions which electrically contact respective first source and drain regions, for first field effect transistors in an integrated circuit. Then, second source and drain regions for second field effect transistors in the integrated circuit are formed. By simultaneously forming landing pads which electrically contact the integrated circuit substrate between first spaced apart gates, and doping the integrated circuit substrate which electrically contacts the landing pads, an additional protective layer may not be needed, thereby simplifying the fabrication process.

REFERENCES:
patent: 4221044 (1980-09-01), Godejahn, Jr. et al.
patent: 4516313 (1985-05-01), Turi et al.
patent: 4992389 (1991-02-01), Ogura et al.
patent: 5183773 (1993-02-01), Miyata

Affiliated with

Also associated with

Rating

Selective landing pad fabricating methods for integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Selective landing pad fabricating methods for integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective landing pad fabricating methods for integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-408574