Secure and static 4T SRAM cells in EDRAM technology

Details Secure and static 4T SRAM cells in EDRAM technology Secure and static 4T SRAM cells in EDRAM technology

2005-05-03

2005-05-03

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S149000, C257S298000

Reexamination Certificate

active

06888741

ABSTRACT:
Disclosed herein is a 4T (four transistor) SRAM cells. Stability, fabrication and integration density advantages as well as a high degree of soft error immunity with small and potentially tailorable write delay penalty may potentially be available in a memory cell by providing a source of pull down current through leakage of stabilizing capacitors, pass gate transistor leakage/off current, or a combination thereof. The source of pull down current allows omission of active pull down devices in a four transistor memory cell circuit to substantially reduce memory cell size or footprint while providing levels of soft error immunity comparable to or exceeding that of known 6T memory cell designs fabricated at comparable minimum feature size regimes and avoiding the expected increase of soft error rates as minimum feature size and/or number of circuit elements is reduced.

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patent: 6707702 (2001-03-01), Komatsuzaki
Kenji Noda, et al., “An Ultrahigh-Density High-Speed Loadless Four-Transistor SRAM Macro with Twisted Bitline Architecture and Triple-Well Shield”, IEEE Journal of Solid-State Circuits, vol. 36, No. 3, Mar. 2001, pp 510-515.

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