Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-08-09
2005-08-09
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06928598
ABSTRACT:
A system and method for protecting the values stored in a BISR repair block and, optionally, debugging the BISR repair logic without altering normal test flow is implemented by a circuit including a plurality of soft latches within the BISR repair block, the soft latches being coupled together to form a BISR scan chain for holding BISR repair information. A chip level scan enable signal and a scan hold control signal cooperate to control connection of the BISR scan chain to other scan chains during a scan test, so that the BSR repair information is held within the soft latches. A diagnose enable signal cooperating with the chip level scan enable signal and the scan hold control signal for enabling debugging of logic connecting the BISR scan chains.
REFERENCES:
patent: 6067262 (2000-05-01), Irrinki et al.
patent: 6212656 (2001-04-01), Fosco et al.
patent: 6408414 (2002-06-01), Hatada
Agrawal Ghasi R.
Puri Mukesh K.
Kerveros James C.
Lamarre Guy J.
Suiter - West PC LLO
LandOfFree
Scan method for built-in-self-repair (BISR) does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scan method for built-in-self-repair (BISR), we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scan method for built-in-self-repair (BISR) will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3473932