Scan flip-flop that simultaneously holds logic values from a...

Details Scan flip-flop that simultaneously holds logic values from a... Scan flip-flop that simultaneously holds logic values from a...

1998-06-16

2001-01-30

De Cady, Albert (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06182256

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to scan flip-flops and, more particularly, to a scan flip-flop that simultaneously holds a logic value shifted into the flop from a serial load, and a logic value loaded into the flop from a subsequent parallel load.
2. Description of the Related Art
The fundamental approach to testing digital logic at the end of a manufacturing line is to apply a series of logic patterns to the input pins, and then evaluate the logic patterns on the output pins to insure that the proper values are present. The series of logic patterns, in turn, are selected so that every path through the logic is exercised.
While simple in concept, the complexity of this approach increases exponentially as the depth of the logic, i.e., the number of gates between the input and output pins, increases. With deep logic, it is often the case that some portion of the logic can not be exercised by simply applying different patterns to the input pins.
One common technique for limiting the depth of the logic is to use a partitioned logic circuit. With a partitioned logic circuit, special test flip-flops, known as scan flip-flops or scan flops, are chained together at regular intervals to divide the logic circuit into a plurality of logic subcircuits.
FIG. 1
shows a block diagram that illustrates a conventional partitioned logic circuit
100
. As shown in
FIG. 1
, logic circuit
100
includes a series of logic subcircuits SC
1
-SCm, and a series of scan flop chains FC
1
-FCn which connect the subcircuits SC
1
-SCm together.
As further shown in
FIG. 1
, the first logic subcircuit SC
1
is connected to a plurality of input pins
102
, while the last logic subcircuit SCm is connected to a plurality of output pins
104
. Each scan flop chain FC, in turn, is positioned between an adjacent pair of subcircuits SC so that each subcircuit SC, except for the first, has a corresponding input chain, and each subcircuit SC, except for the last, has a corresponding output chain.
For example, flop chain FC
1
functions as the output chain for subcircuit SC
1
, and the input chain for subcircuit SC
2
, while flop chain FC
2
functions as the output chain for subcircuit SC
2
, and the input chain for subcircuit SC
3
. (Flop chains are typically not required to input test patterns into the first subcircuit, or to output patterns from the last subcircuit as these functions are provided by the testing equipment).
In addition, each scan flop chain FC includes a plurality of scan flops
110
which each have a parallel input
112
, a parallel output
114
, a serial input
116
, and a serial output
118
. As shown, the outputs from a subcircuit SC are connected to the parallel inputs
112
of the flops
110
in the corresponding output chain, while the inputs to a subcircuit SC are connected to the parallel outputs
114
of the flops
110
in the corresponding input chain. Further, the serial inputs and outputs
116
and
118
are utilized to serially connect the flops
110
in a flop chain FC.
FIGS. 2A-2D
show block diagrams that illustrate the operation of partitioned logic circuit
100
.
FIGS. 2A-2D
are similar to
FIG. 1 and
, as a result, utilize the same reference numerals to designate the common structures.
FIG. 3
shows a timing diagram that further illustrates the operation of circuit
100
.
In operation, logic circuit
100
functions in a logic mode and a test mode. When in the logic mode, logic signals are clocked through the scan flops
110
in a manner which allows logic circuit
100
to function as a single logic device.
Prior to entering the test mode, a series of test patterns is selected for each subcircuit SC so that, when the test patterns are applied to the subcircuits SC, all of the logic paths through the subcircuits SC are exercised. For example, as shown in
FIG. 2A
, test patterns FP
1
-FPr, SP
1
-SPr, TP
1
-TPr, and LP
1
-LPr have been selected for subcircuits SC
1
, SC
2
, SC
3
, and SCm, respectively.
When in the test mode, the first test pattern FP
1
is presented to the parallel inputs of the first subcircuit SC
1
, while the first test patterns SP
1
, TP
1
, and LP
1
are serially loaded into flop chains FC
1
, FC
2
, and FCn, respectively.
For example, as shown in
FIG. 2B
, first test pattern [1-0-0- . . . -0] is presented to subcircuit SC
1
, while first test patterns [0-1-0- . . . -1], [0-0-0- . . . -1], and [1-0-0- . . . -1] are serially loaded into flop chains FC
1
, FC
2
, and FCn, respectively.
The last logic values of the first test patterns are serially loaded into the flop chains FC on the rising edge of clock cycle A as shown in FIG.
3
. After this, during clock cycle A, each first test pattern propagates through the corresponding subcircuit SC, and causes a first new logic pattern to be presented to the corresponding output chains and the output pins
104
.
For example, as further shown in
FIG. 2B
, first test pattern [1-0-0- . . . -0] , which was presented to subcircuit SC
1
, causes a first new logic pattern [1-1-0- . . . -0] to be presented to flop chain FC
1
, while first test pattern [0-1-0- . . . -1], which was loaded into flop chain FC
1
, causes a first new logic pattern [1-1-1- . . . -0] to be presented to flop chain FC
2
.
Similarly, first test pattern [0-0-0- . . . -1], which was loaded into flop chain FC
2
, causes a first new logic pattern [0-1-0- . . . -1] to be output from subcircuit SC
3
, while first test pattern [1-0-0- . . . -1] , which was loaded into flop chain FCn, causes a first new logic pattern [0-0-1- . . . -0] to be output from subcircuit SCm.
Following this, on the rising edge of clock cycle B, which is known as the parallel load cycle, flop chains FC
1
-FCn latch the first new logic patterns output from subcircuits SC
1
-SCm via the parallel inputs
112
.
For example, as shown in
FIG. 2C
, the first new logic pattern [1-1-0- . . . -0] output from subcircuit SC
1
is latched by flop chain FC
1
. Similarly, the first new logic pattern [1-1-1- . . . -0] output from subcircuit SC
2
is latched by flop chain FC
2
, and the first new logic pattern [0-1-0- . . . -1] output from subcircuit SC
3
is latched by flop chain FCn (assuming only four subcircuits).
Once latched, these first new logic patterns also propagate through the following logic subcircuits SC, and cause a second new logic pattern to be presented to the parallel inputs
112
of the flop chains FC
1
-FCn, and output on the output pins
104
.
For example, as shown in
FIG. 2C
, the first new logic pattern [1-1-0- . . . -0] that was latched by flop chain FC
1
now causes a second new logic pattern [1-0-1- . . . -0] to be presented to the parallel inputs of flop chain FC
2
.
Similarly, the first new logic pattern [1-1-1- . . . -0] latched by flop chain FC
2
causes a second new logic pattern [0-0-0- . . . -1] to be output from subcircuit SC
3
, while the first new logic pattern [0-1-0- . . . -1] latched by subcircuit SCm causes a second new logic pattern [0-0-0- . . . -0] to be output to pins
104
. (Note that the logic pattern presented at the parallel inputs to flop chain FC
1
does not change because the test pattern FP
1
has not yet changed).
Next, at time t
3
in clock cycle B, the test equipment latches the second new logic pattern output from subcircuit SCm, (e.g., logic pattern [0-0-0- . . . -0]). After this, on the rising edge of clock cycle C, the second test pattern FP
2
is presented to the first subcircuit SC
1
, while the first values of the second test patterns SP
2
, TP
2
, and LP
2
are serially loaded into flop chains FC
1
, FC
2
, and FCn, respectively.
The serial load process continues until second test patterns SP
2
, TP
2
, and LP
2
are serially loaded into flop chains FC
1
, FC
2
, and FCn, respectively. Thus, as shown in
FIG. 2D
, second test pattern [1-0-1- . . . -1] is

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