Scalable MOS field effect transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438301, 438586, H01L 218238

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active

060965908

ABSTRACT:
A field effect transistor and method for making is described incorporating self aligned source and drain contacts with Schottky metal-to-semiconductor junction and a T-shaped gate or incorporating highly doped semiconductor material for the source and drain contacts different from the channel material to provide etch selectivity and a T-shaped gate or incorporating a metal for the source and drain contacts and the oxide of the metal for the gate dielectric which is self aligned. The invention overcomes the problem of self-aligned high resistance source/drain contacts and a high resistance gate electrode for submicron FET devices which increase as devices are scaled to smaller dimensions.

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A. Acovic et al., "Novel Gate Process for 0.1 Micron MOSFETs", IBM Technical Disclosure Bulletin, vol. 36, No. 11, Nov. 1993.

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