Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-05-15
2009-12-22
Dang, Trung (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S288000, C257SE21423
Reexamination Certificate
active
07635630
ABSTRACT:
A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non-volatile memory cell is formed on each sidewall of the trench. Each memory cell is comprised of a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks. In one embodiment, each gate insulator stack is comprised of a tunnel insulator formed over the sidewall, a deep trapping layer, and a charge blocking layer. In another embodiment, an injector silicon rich nitride layer is formed between the deep trapping layer and the charge blocking layer.
REFERENCES:
patent: 6710404 (2004-03-01), Lee
patent: 6717200 (2004-04-01), Schamberger et al.
patent: 6781197 (2004-08-01), Fujishima et al.
patent: 7075146 (2006-07-01), Forbes
patent: 7109551 (2006-09-01), Sugi et al.
patent: 7148538 (2006-12-01), Forbes
patent: 7241654 (2007-07-01), Forbes
patent: 2002/0175365 (2002-11-01), Hirayama
patent: 2004/0004859 (2004-01-01), Forbes et al.
patent: 2004/0202032 (2004-10-01), Forbes
patent: 2005/0001264 (2005-01-01), Ono et al.
patent: 2005/0285175 (2005-12-01), Cheng et al.
patent: 2006/0013042 (2006-01-01), Forbes et al.
patent: 2006/0131633 (2006-06-01), Bhattacharyya
patent: 2006/0220093 (2006-10-01), Van Schaijk et al.
patent: 2009/0173985 (2009-07-01), Lee et al.
H. Kotaki,70nm High-Performance 2 bit/cell Nonvolatile Memory with Oxide/Nitride/Oxide Sidewalls, Sharp Corporation, Nara, Japan, 2003, 3 pgs.
T. Ishimaru et al.,Impact of SiON on Embedded Nonvolatile MNOS Memory, Hitachi, Ltd., Renesas Technology Corp., Tokyo, Japan, 2004, 3 pgs.
Dang Trung
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
LandOfFree
Scalable high density non-volatile memory cells in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scalable high density non-volatile memory cells in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scalable high density non-volatile memory cells in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4107538