Deferring refreshes during calibrations in memory systems

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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C711S105000, C711S154000, C365S222000

Reexamination Certificate

active

07613873

ABSTRACT:
A memory system employs calibrations to ensure the precise transmission of data. During calibrations, memory refreshes can occur; however, these refreshes can interfere with calibration streams. Therefore, to alleviate collisions and interferences, refreshes are deferred to periods where no calibrations are taking place. The number of deferred refreshes is also tracked such that the overall loss of refreshes is prevented.

REFERENCES:
patent: 6310814 (2001-10-01), Hampel et al.
patent: 6496437 (2002-12-01), Leung
patent: 6560155 (2003-05-01), Hush
patent: 6931484 (2005-08-01), Ranganathan et al.
patent: 2001/0040833 (2001-11-01), Bogin et al.

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