Metal fusion bonding – Process – With protecting of work or filler or applying flux
Reexamination Certificate
2002-02-19
2003-09-23
Dunn, Tom (Department: 1725)
Metal fusion bonding
Process
With protecting of work or filler or applying flux
C228S180220, C228S245000, C228S256000, C438S613000, C438S694000, C216S018000, C216S041000
Reexamination Certificate
active
06622907
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to processes for forming C
4
solder bumps and more particularly to the metallurgy employed for enhanced characteristics of the joints.
2. Description of Related Art
Controlled Collapse Chip Connection (C
4
) solder ball, flip chip connections have been used for more than thirty years to provide flip chip interconnections between semiconductor devices and substrates. Cylindrical C
4
solder bumps are formed above an insulation layer and above the exposed surfaces of connector pads each of which is exposed through a VIA hole in the insulation layers. Later the C
4
solder bumps are heated above the melting point until the C
4
solder bumps reflow by controlled collapse to form C
4
solder balls. The actual C
4
solder bumps may be fabricated using a number of different processing techniques, including evaporation, screening, and electroplating. Fabrication by electroplating requires a series of basic steps which typically include but are not limited to the deposition of a metallic seed layer on the top surface of the wafer final passivation layer, the application of an imaged photoresist (in the pattern of C
4
solder bumps), the electrodeposition of solder, the stripping of the photoresist, and the subetching of the metallic seed layer to isolate the C
4
bumps. The metallurgy which is chosen for the seed layer is crucial to both the fabrication process and the ultimate C
4
structure.
The first fundamental operation in forming C
4
solder bumps by electrolytic means is to deposit a continuous stack of metal films across the wafer to be bumped. The so-called “conductive metal” performs a dual function. First, it provides a conductive path for current flow during the electrolytic deposition of the C
4
solder bumps. Second, the conductive metal remains under the C
4
solder bumps and forms the basis for the Ball Limiting Metallurgy (BLM) underneath the C
4
solder balls, which ultimately defines the field reliability of the device. Therefore, the BLM layers must include at least one layer that is conductive enough to permit uniform electrodeposition across the entire expanse of the wafer. The bottom layer must adhere well to the underlying passivation, and the top layer must interact sufficiently with the solder to form a reliable bond. In addition, the BLM may contain barrier layers which prevent the solder from detrimentally interacting with the underlying device constituents. Finally, the stresses generated by the composite seed layer stack should be low enough to sustain the reliability of C
4
solder ball joints when exposed to various thermo-mechanical stresses. As a result, both the constituents and the thicknesses of the various BLM layers (i.e. barrier layer and seed layer metals) are carefully chosen to provide sufficient functionality under a wide variety of thermal, mechanical and environmental conditions.
Because of its relatively high conductivity, copper (Cu) is used frequently as an electroplating conductive metal. This method has proven successful for C
4
solder bump applications, when including a layer of copper in the seed layer stack greater than 1000 Angstroms in thickness), provides adequate conductivity to electroplate C
4
solder bumps uniformly across an entire 300 mm diameter wafer. In many cases, particularly those in which the C
4
solder bumps contain a high percentage of lead (Pb) metal (greater than 90% Pb), the presence of copper in the BLM metal layers also satisfies the other objectives listed above. Upon heat treatment, lead-rich C
4
solder bumps containing small amounts of tin beneficially react with the copper layer to form stable copper tin (Cu—Sn) intermetallic compounds that remain intact over a wide range of field conditions.
However, there are more recent applications in which it can actually be detrimental to include copper as a BLM constituent of the seed layer. Many semiconductor packages now utilize organic carriers, which cannot tolerate temperatures in excess of 240° C. In addition, many high performance semiconductor devices are now being designed with low K dielectric materials that become unstable at temperatures above 300° C. Finally, there is a strong market demand for lead-free solders, which are gradually being introduced as high-Sn composites. For these reasons, high-lead solder bumps that melt at temperatures greater than 300° C. are not universally applicable. As a result, C
4
solder bumps which contain higher percentages of tin and melt at temperatures less than 220° C. are becoming industry standard.
High-Sn C
4
's are easily fabricated by electrodeposition, provided that a sufficiently conductive seed layer such as copper is employed. Unfortunately, the presence of copper in the final BLM structure does not necessarily produce a reliable structure. Upon heat treatment, copper reacts so aggressively in the presence of Sn-rich solder bumps that a BLM structure containing copper becomes unstable and deteriorates rapidly. One way to mitigate this effect is to utilize copper as a conductor, but protect it with a less reactive barrier layer, such as Ni. This solution does minimize exposure to BLM attack, but under extreme field conditions, the high-Sn solder has the potential to eventually attack the copper portion of the BLM from the periphery of the C
4
solder balls. Completely removing copper from the seed layer is plausible, but renders it extremely difficult to electroplate C
4
solder balls uniformly without a sufficiently conductive seed layer.
FIGS. 1A and 1B
illustrate a prior art process for manufacturing one or more C
4
solder bump(s)
24
and forming one or more C
4
solder balls
30
therefrom on a conformal, seed layer stack
15
formed above a metal contact
11
formed on a semiconductor device
10
. The seed layer stack
15
is composed of a base of at least one metal adhesion layer
16
. As shown in
FIGS. 1A and 1B
the device
10
includes a base of two metal layers
16
/
20
. To complete the seed layer stack, the metallic base layers
16
/
20
are covered by a conductive metal (CM) layer
22
, that is composed of copper (Cu). A portion of the semiconductor device
10
is shown to illustrate an example of a C
4
bumping process sequence in which the seed layer stack
15
is used during processing. As will be explained below, after processing only a portion of the copper originally included in CM layer
22
remains in CM layer
22
N as a part of the seed layer stack
15
of layers
16
N,
20
N and
22
N in FIG.
1
B.
The device
10
on which the seed layer stack
15
and the C
4
solder bump
24
are formed includes a lower insulator layer
12
in which the metal contact
11
has been formed. The metal contact
11
is partially covered by a second insulator layer
14
through which a tapered VIA hole has been formed exposing a portion of the top surface of the metal contact
11
. The seed layer stack
15
is formed on the surfaces of the second insulator layer
14
and the exposed portion of the top surface of the metal contact
11
. The C
4
solder bump
24
is formed over the seed layer stack
15
in an opening formed in a photoresist mask PR′.
The series of process steps used to fabricate structures in FIGS.
1
A and lB begins with a partially formed device
10
which includes the planar contact
11
and the lower insulation layer
12
, which have been formed on the surface a substrate
9
, such as a silicon wafer (as shown) or a dielectric layer formed thereabove, as will be well understood by those skilled in the art. The contact and the lower insulation layer
12
are shown as having upper surfaces which are formed in a single plane. An upper insulation layer
14
is formed covering both a portion of the planar contact
11
and the lower insulation layer
12
with a tapered VIA hole opening through the upper insulation layer
14
exposing a portion of the top surface of the contact
11
.
The processing sequence is as follows:
1. Deposit a multi-layer, conformal, seed layer stack
15
on the surface of insul
Fanti Lisa A.
Knarr Randolph F.
Roggeman Erik J.
Srivastava Kamalesh K.
Blecker Ira D.
Dunn Tom
Jones II Graham S.
Stoner Kiley
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