Sacrificial metal spacer damascene process

Details Sacrificial metal spacer damascene process Sacrificial metal spacer damascene process

2005-01-25

2005-01-25

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S639000, C438S687000

Reexamination Certificate

active

06846741

ABSTRACT:
A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs.

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