RTP process chamber pressure control

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S513000

Reexamination Certificate

active

06828234

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductor manufacturing. More specifically, the present invention relates to the process environment within a single wafer process chamber.
2. Description of the Related Art
Rapid Thermal Processing, commonly referred to as “RTP,” subjects the wafer to a very brief, intense burst of heat that can go from room temperature to 1000° C. in seconds. This technology is used to change the characteristics of a deposited film or a crystal lattice. With the short, fast-ramping temperature cycling of RTP, variations among systems can potentially have a large impact on process results, which in turn can affect device speed and reliability. The most common use for an RTP chamber is for annealing, which activates and controls the movement of atoms in the device after implanting. Another common use is for silicidation, which uses heat to form silicon-containing compounds with metals such as tungsten or titanium. A third type of RTP application is oxidation, which involves growing oxide on the wafer.
Rapid Thermal Processing (RTP), a high-temperature technology, uses very rapid, precise heating to improve the properties of deposited films. RTP replaces conventional technologies that heat the wafer slowly in large batches.
Ion implantation provides precise control of electrical currents within specific layers of a semiconductor chip. An ion beam accelerates dopant ions in a way that permits them to penetrate the semiconductor's crystalline structure to a desired depth without damaging other sensitive circuitry on the wafer. Thermal annealing is the process that occurs after the implantation step in integrated circuit fabrication. Its function is to repair damage on silicon wafers and to activate implanted impurities.
As the industry moves to extremely short anneal times in advanced devices, the process of ramping up and cooling down account for a significant fraction of the total process time and thus control overall process results. The formation of ultra-shallow junctions, for example, requires precise, rapid (spike) implant anneals that limit high temperature exposure of the wafer to a few seconds. To enable these new device designs, the process chambers will require significant advancements in process control, even at high temperature ramp rates, for exceptional within-wafer uniformity and wafer-to-wafer repeatability.
Single wafer systems having fast wafer rotation (240 rpm) and a high speed (100 Hz), multi-point, closed-loop temperature control system provides tight temperature uniformity during ramps. Rapid ramp (250° C./s) and cool-down (90° C./s) rates limit thermal exposure of the wafer to less than 3 seconds above 950° C. for a 1050° C. spike anneal. Such process controls enable closed loop control at process temperatures below 280° C. for next-generation cobalt or nickel silicides. These new systems can be quickly qualified and calibrated, while process recipe setup, matching, and transfer are also much improved. Operators can tune the process and cut setup cost dramatically with the new system. Enhanced temperature uniformity across the wafer can improve yield by permitting better control of device parameters as well as gate oxide thickness and uniformity at sub-angstrom levels. Such control systems can feature integrated multi-point temperature measurement and emissivity compensation. These features improve overall temperature uniformity over the entire range of wafer backside emissivities; this is especially important where multiple types of devices are manufactured.
FIG. 1
is an illustration of a process chamber used for RTP. The process chamber, used for annealing and/or oxidation applications, can have problems with oxygen contamination from the atmosphere. To process wafers, for example, in a thermal process, a chamber is provided with a support ring to hold a wafer at the wafer edge, i.e. an edge ring. The edge ring can be configured to receive a wafer and the edge ring and wafer can be rotated by a quartz cylinder base. The reflector plate can be positioned beneath the edge ring to improve heating efficiency by providing a degree of black body absorption by the wafer. Fiber optic probes can measure wafer temperatures at different locations. The wafer is typically placed onto and removed from the edge ring by a robot blade and supported by the edge ring during processing. In typical prior art systems, the edge ring and the wafer are heated to a temperature of between 200-650° C. prior to processing by halogen lamps that are placed into a water-cooled housing and where the lamps are separated from the process area by thin quartz windows. Once the wafer is heated to an appropriate temperature, a processing gas is introduced into the chamber through a gas manifold often situated above the wafer. The processing gas can be inert or reactive, and if reactive, the gas can then react with the wafer surface.
A first goal of wafer processing is to obtain as many useful dies as possible from each wafer. Many factors affect the ultimate yield of die from each wafer processed. These factors include processing variables, which affect the uniformity and thickness of the material layer deposited on the wafer, and particulate and oxide contaminants that can attach to a wafer and contaminate one or more die. Both of these factors must be controlled in RTP and other processes to maximize the die yield from each wafer.
SUMMARY OF THE INVENTION
A method for reducing contaminates in the ambient atmosphere from flowing into the interior of an RTP single wafer process chamber during a wafer transfer. The method maintains positive pressure within the process chamber relative to atmospheric pressure by the flow an inert gas into the process chamber during the wafer transfer.


REFERENCES:
patent: 6348420 (2002-02-01), Raaijmakers et al.
patent: 6362086 (2002-03-01), Weimer et al.
patent: 6544900 (2003-04-01), Raaijmakers et al.
patent: 6596595 (2003-07-01), Weimer et al.

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