Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-02-03
2001-05-22
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S222000, C365S233100
Reexamination Certificate
active
06236604
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a row address circuit of a semiconductor memory device such as a DRAM and to row addressing in a refresh mode of the DRAM.
2. Description of Related Art
Generally, a semiconductor memory device such as a DRAM stores data as electric charge in isolated cell capacitors. However, leakage current from a capacitor can change the charge and destroy the stored data. Accordingly, DRAMs require periodic refresh operations that read and rewrite the stored data and thereby refresh the charge stored on the cell capacitors. Refresh operations are thus very important in a DRAM. Current DRAMs commonly adopt a CAS-Before-RAS automatic refresh method. With this refresh method, a refresh address counter built into a DRAM chip generates a row address, and the DRAM does not require an externally generated refresh address. When operating in the refresh mode, the DRAM uses the internally generated row addresses and disables use of externally input addresses. There are two common methods for disabling use of the externally generated address. One method operates a transfer gate of an address input circuit to cut off the input of an external address when a refresh count signal is in an active state. The other method disables changes in the output of a predecoder to prevent the output of a predecoded row address from changing based on the externally input address when the refresh count signal is inactive.
Conventionally, a semiconductor device uses a row address setup signal as a control signal of a transfer gate in the input stage of a predecoder. The row address setup signal enables and disables input of an external row address in a normal operating mode of the DRAM.
In the refresh mode, a delayed refresh count signal enables and disables input of the refresh row address from the counter. The delayed refresh count signal is commonly delayed to match the timing of the row address setup signal. Accordingly, immediately after a transition of the refresh count signal, an external address can change the row address before the delayed refresh count signal disables the transfer gates. This allows the predecoded row address signal to change with the result that two word lines are enabled or an invalid address is generated.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, a row address circuit of a semiconductor memory device and a row addressing method used in the row address circuit prevent an invalid address from arising in a refresh mode. More specifically, the row address circuit cuts off changes in an output signal of a predecoder before a corresponding transition of a refresh count signal might allow a change of the output signal.
A semiconductor device according to one embodiment of the present invention includes a refresh address counter, an input circuit, a predecoder, a signal generator, an output generator, and a precharge circuit. The refresh address counter changes a refresh address signal in response to a leading edge of an active region of a refresh count signal. The input circuit selectively inputs an external signal in normal mode or the refresh address signal in a refresh mode. The predecoder inputs and predecodes the row address signal from the input circuit in response to a row address setup signal in the normal mode and in response to a delayed refresh count signal in the refresh mode. The signal generator produces an enable signal having a leading edge delayed relative to a leading edge of an active region of the refresh count signal and a trailing edge before a trailing edge of the active region of the refresh count signal. The signal generator generates the enable signal in response to the refresh count signal in the refresh mode. The output generator can change the predecoded row address signal during the active region of the enable signal. The precharge circuit precharges an input edge of the predecoder in response to a trailing edge of the enable signal.
An addressing method according to the present invention includes: generating a refresh address signal in response to a trailing edge of an active region of a refresh count signal; opening an input passage for the refresh address signal and cutting off an input passage of an external address signal at the trailing edge of the active region of the refresh count signal; predecoding the refresh row address signal in response to a delayed refresh count signal; generating an enable signal having a leading edge delayed relative to a leading edge of the active region of the refresh count signal and a trailing edge occurring before the trailing edge of the active region of the refresh count signal; outputting the predecoded row address signal in response to a leading edge of the enable signal; and precharging an input stage of the predecoder in response to a trailing edge of the enable signal.
Further aspects and advantage of the invention can be more fully understood from the following detailed description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5430680 (1995-07-01), Parris
patent: 5978297 (1999-11-01), Ingalls
patent: 5999481 (1999-12-01), Cowles et al.
Bae Il Man
Hong Sang Pyo
Heid David W.
Le Vu A.
Nguyen Hien
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
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