Robust latchup-immune CMOS structure

Details Robust latchup-immune CMOS structure Robust latchup-immune CMOS structure

1999-01-11

2001-02-20

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S371000, C257S372000

Reexamination Certificate

active

06190954

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to methods of fabricating integrated CMOS circuits, and more particularly to making a CMOS twin-well integrated circuit more immune to latchup due to parasitic transistors.
2. Description of the Related Art
Latchup is a phenomenon of CMOS circuits and is well described by S. Wolf in
Silicon Processing for the VLSI Era,
Volume 2, by Lattice Press, copyright 1990, 6.4 LATCHUP IN CMOS, page 400: “A major problem in CMOS circuits is the inherent, self-destructive phenomenon known as latchup. Latchup is a phenomenon that establishes a very low-resistance path between the V
DD
and V
SS
power lines, allowing large currents to flow through the circuit. This can cause the circuit to cease functioning or even to destroy itself (due to heat damage caused by high power dissipation).
The susceptibility to latchup arises from the presence of complementary parasitic bipolar transistor structures, which result from the fabrication of the complementary MOS devices in CMOS structures. Since they are in close proximity to one another, the complementary bipolar structures can interact electrically to form device structures which behave like pnpn diodes.”
FIG. 1
shows a cross-sectional view of a twin-well CMOS arrangement in a p-substrate
11
with an n-well
12
, having a p
+
source
13
connected to an n
+
pad
14
,
13
and
14
connected to a supply voltage
15
(+)V
dd
, and a p-well
16
showing an n
+
source
17
connected to a p
+
pad
18
,
17
and
18
connected to a reference voltage (−)V
ss
, typically ground. The drain of the p-channel (PMOS) transistor in n-well
12
is not shown nor is shown the drain of the n-channel (NMOS) transistor in p-well
16
. Q
1
is a lateral pnp parasitic transistor structure and Q
2
is a vertical npn parasitic transistor structure which results from the arrangement of NMOS and PMOS transistors. The lateral transistor Q
1
comprises the source
13
of the PMOS transistor (emitter), n-well
12
(base), and p-substrate
11
(collector). The vertical transistor Q
2
comprises source
17
of the NMOS transistor (emitter), p-well
16
(base), and n-well
12
(collector). N-well current flows from
15
(+)V
dd
through n-well
12
having a resistance R
NW
, to the collector of Q
2
. P-well current flows from the collector of Q
1
through p-substrate
11
, through p-well
16
,
16
having resistance R
PW
, to
19
(−)V
ss
.
FIG. 2
, is an equivalent circuit diagram of the parasitic transistors of FIG.
1
. The region of each transistor terminal is identified by a circle with an “n” or a “p”. In this circuit the base of each transistor is connected to the collector of the other transistor. Inspection of
FIG. 2
shows that this circuit is the equivalent of a parasitic pnpn diode (from emitter of Q
1
to emitter of Q
2
). A pnpn diode below a certain “trigger” voltage acts as a high impedance, but when biased beyond that “trigger” voltage will act as a low impedance device similar to a forward biased diode. This results in a current that depends on R
NW
and R
PW
and can be destructive to the CMOS circuit.
FIG. 3
a
shows the same arrangement as that of
FIG. 1
, where like numerals indicate like members, except that a trench
31
between n-well
12
and p-well
16
was added as a means of implementing n
+
-to-p
+
isolation structures primarily for achieving smaller interwell (n
+
-to-p
+
) isolation spacing. Deep trenches were also expected to solve or reduce latchup problems, however, they have not been as successful as hoped. Refer to S. Wolf in
Silicon Processing for the VLSI Era,
Volume 3, by Lattice Press, copyright 1995, 6.6.7 Trench Isolation for CMOS.
FIG. 3
b
and
FIG. 3
c
show the standard energy band diagram for a pnp and npn transistor, respectively, as relating to the parasitic transistors Q
1
and Q
2
of
FIGS. 1 and 2
, where Curve
32
indicates the intrinsic Fermi level E
i
.
Many workers have tackled the problem of latchup with various degrees of success, but the problem of latchup keeps on surfacing as transistor dimensions shrink to quarter and sub-quarter micron dimensions, because of the reduced well depth and inter-well spacing.
U.S. Pat. No. 5,675,170 (Kim) shows an n-well guard ring to interrupt the movement of minority carriers from the drain of an n-channel transistor to the n+pickup region of a p-channel transistor, thus preventing latchup.
U.S. Pat. No. 5,563,438 (Tsang) teaches the use of a third region adjacent to the drain region on the opposite side of the source. This third region is doped to have a polarity opposite to that of the drain and forms in combination with the drain an output protect diode, rendering the transistor relatively free of latchup.
U.S. Pat. No. 5,138,420 (Komori et al.) discloses the use of a p
+
deep well trench between an n-well and a p-well to prevent latchup.
It should be noted that none of the above-cited examples of the related art offer the simplicity and ease of providing a robust latchup-immune CMOS structure as does the proposed invention which will be discussed in detail in the Description of the Preferred Embodiment.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for a more robust latchup-immune integrated circuit structure.
Another object of the present invention is to provide a method to increase the breakover voltage V
BO
, or trigger point, of the parasitic npn and pnp transistors present in a CMOS structure.
These objects have been achieved by adding a barrier layer to the n-well and p-well of a twin-well CMOS structure, thus increasing the energy gap for both electrons and holes of the parasitic npn and pnp transistors, respectively.


REFERENCES:
patent: 5138420 (1992-08-01), Komori et al.
patent: 5563438 (1996-10-01), Tsang
patent: 5675170 (1997-10-01), Kim
patent: 5831313 (1998-11-01), Han et al.
patent: 5956591 (1999-09-01), Fulford, Jr.
patent: 5966598 (1999-10-01), Yamazaki
Wolf, “Silicon Processing for the ULSI Era”, vol. 2, Lattice Press, 1990, pp. 400-413.
Wolf, “Silicon Processing for the VLSI Era”, vol. 3, Lattice Press, 1995, pp. 406-413.

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