Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-07-18
2006-07-18
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07080299
ABSTRACT:
Within an integrated circuit2a functional block of circuitry6has an associated test wrapper circuit10. The functional block of circuitry6includes functional latches14at least some of which may also serve as shared test latches18within the test wrapper circuitry10. Separate reset signals reset_wrp, reset_int are generated for the test latches and shared test latches18as distinct from the functional latches14. Thus, during testing, power consuming activity of the functional latches14can be suppressed if it is not desired to test the functional block of circuitry6itself. This is a particularly useful technique when a functional block of circuitry6is required to operate in an extest mode in which output signals from it are required to be driven so that other elements in the overall design may be tested and yet the internal action of the functional block of circuity6is not under test.
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“Wrapper Design for Embedded Core Test” by Marinissen et al. This paper appears in International Test Conference Proceedings Publication Date: 2000 pp. 911-920 INSPEC Accession No.: 6859181.
ARM Limited
Britt Cynthia
Lamarre Guy
Nixon & Vanderhye P.C.
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