Resettable memory structure

Details Resettable memory structure Resettable memory structure

1999-07-15

2001-05-08

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189120

Reexamination Certificate

active

06229738

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to memory structures embedded in integrated circuits, in particular to registers in application specific integrated circuits (ASIC).
DESCRIPTION OF RELATED ART
Registers embedded in application specific integrated circuits are typically realised using latches or flip-flops. The design of a memory embedded in an application specific integrated circuit, in which the reset state of each bit can be arbitrarily set to ‘1’ or ‘0’ in the design phase is difficult and the result is complex and space-consuming.
The problem with a latch circuit equipped with an asynchronous reset input is that ASIC component libraries not always include such elements. If a component library does include such an element, latch circuits settable to both ‘1’ and ‘0’ states are typically not available in one and the same library. If one wants to use a resettable latch circuit in order to realise a memory bit resettable into a logic one, the latch circuit has to be surrounded with two inverters, one before the latch circuit and another after the latch circuit on the latch circuit's datapath. Such a construction increases space consumption. Furthermore, a resettable latch circuit usually is one gate bigger than a latch circuit without a reset input, and the distribution of the reset control signal to the latch circuits requires space.
If all memory elements could be reset into the same state (‘1’ or ‘0’), latch circuits without reset inputs could be used as memory elements, and the setting or reset states could be carried out by forcing the latch circuits transparent for the duration of the reset state so that the state of the data bus brought to the latch circuits would appear at the outputs of the latch circuits, and by forcing the bus into the desired state. Such a construction, however, does not meet the requirement of an arbitrary reset state.
A resettable memory can also be realised using flip-flops, or clocked edge-triggered elements. A resettable flip-flop in accordance with good design practice which has a 2:1 multiplexer for input data, as required by the scan test method, and a synchronous enable multiplexer takes about 20 gates in a gate array circuit implemented with CMOS technology. Furthermore, reset and scan enable controls have to be brought to each such element, requiring both wiring space and buffering. Space consumption could be reduced by leaving out functions, but a flip-flop always takes more space than a latch.
SUMMARY OF THE INVENTION
An object of the invention is to provide a structure for realising a memory embedded in an ASIC in which each bit can upon reset be arbitrarily set into either ‘0’ or ‘1’. Another object of the invention is to realise such a structure which is smaller and simpler than the solutions in the prior art and requires fewer gates in the ASIC.
These and other objects of the invention are achieved by realising the memory bits with latch circuits without reset inputs, duplicating the memory structure's input bus, adding to both buses switch elements which in the reset state force all lines of one bus to ‘0’ and all lines of the other bus to ‘1’, and by connecting each latch circuit to one of the buses according to the desired value in the reset state.
The memory structure according to the invention is characterised in that it comprises at least one switch element connected between a certain line on the memory structure's data bus and a corresponding line on at least one memory element's data bus, said switch element being such that in response to a reset signal it connects a predetermined value to said memory element's input line.
The structure according to the invention uses a latch circuit without a reset input as a structural unit for memory. The memory structure's input bus is duplicated, and the first bus is forced to have the value “0000” in the reset state, and the second bus is forced to have the value “1111”. In the reset state the latch circuits are forced transparent so that the reset state of each memory bit depends on which of the buses the latch circuit is connected to. The structure according to the invention fulfills the requirement of an arbitrarily selectable reset state while at the same time the memory can be realised using the smallest possible elements, i.e. latch circuits without reset inputs.


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Patent Abstracts of Japan, vol. 12, No 38, E-580 abstract of JP 62-190917 A (NEC Corp.), Aug. 21, 1987.

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