Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-07-30
2010-11-23
Nguyen, Ha Tran T (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S421000, C438S595000, C257S386000, C257SE21626, C257SE21640
Reexamination Certificate
active
07838373
ABSTRACT:
A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact.
REFERENCES:
patent: 5960270 (1999-09-01), Misra et al.
patent: 6808982 (2004-10-01), Parekh et al.
patent: 7132342 (2006-11-01), Sadovnikov et al.
patent: 7585716 (2009-09-01), Cheng
Giles Martin
Kavalieros Jack
Rachmady Willy
Rakshit Titash
Shifren Lucian
Greaves John N.
Intel Corporation
Nguyen Ha Tran T
Whalen Daniel
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