Removing the effects of unknown test values from compacted...

Details Removing the effects of unknown test values from compacted... Removing the effects of unknown test values from compacted...

2008-07-01

2008-07-01

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000

Reexamination Certificate

active

07395473

ABSTRACT:
Methods, apparatus, and systems for filtering compacted test responses are disclosed. The methods, apparatus, and systems can be used, for example, to remove the effects of unknown test values. For instance, in one embodiment, a compacted test response from a compactor of a circuit-under-test is received. In this embodiment, the compacted test response includes one or more compacted test response values that are dependent on one or more respective unknown values. The compacted test response is filtered to remove the dependency of at least some of the compacted test response values on the one or more respective unknown values, and a filtered test response is output. Various filtering circuits and testing systems are also disclosed.

REFERENCES:
patent: 6463561 (2002-10-01), Bhawmik et al.
patent: 6557129 (2003-04-01), Rajski et al.
patent: 6590929 (2003-07-01), Williams
patent: 6829740 (2004-12-01), Rajski et al.
patent: 7058869 (2006-06-01), Abdel-Hafez et al.
patent: 7185253 (2007-02-01), Mitra et al.
patent: 7222277 (2007-05-01), Wang et al.
patent: 7239978 (2007-07-01), Cheng et al.
patent: 2003/0188269 (2003-10-01), Mitra et al.
patent: 2004/0230884 (2004-11-01), Rajski et al.
patent: 2005/0055613 (2005-03-01), Mitra et al.
Barnhart et al., “OPMISR: The foundation for compressed ATPG vectors,”Proc. ITC, pp. 748-757 (2001).
Bayraktaroglu et al., “Test volume and application time reduction through scan chain concealment”Proc. IEEE Design Automation Conf., pp. 151-155 (2001).
Blahut, “Linear Block Codes,” inAlgebraic Codes for Data Transmission, Ch. 3, pp. 49-66 (2003).
Blahut,Theory and Practice of Error Control Codes, 7 pp. (May 1983).
Chakrabarty et al., “Test Response Compaction Using Multiplexed Parity Trees,”Proc. Trans. CAD, vol. 15, No. 11, pp. 1399-1408 (Nov. 1996).
Chakrabarty, “Zero-aliasing space compaction using linear compactors with bounded overhead,”Proc. Trans. CAD, vol. 17, pp. 452-457 (May 1998).
Chandra et al., “Frequency-Directed Run Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression,”Proc. VLSI Test Symp., pp. 42-47 (2001).
Chickermane et al., “Channel Masking Synthesis for Efficient On-Chip Test Compression,”Proc. ITC, pp. 452-461 (2004).
Hamzaoglu et al., “Reducing test application time for full scan embedded cores,”Proc. Int. Symp. Fault-Toler. Comput., pp. 260-267 (1999).
Jas et al., “Virtual Scan Chains: A Means for Reducing Scan Length in Cores,”Proc. VLSI Test Symp., pp. 73-78 (2000).
Koenemann et al., “A SmartBIST variant with guaranteed encoding,”Proc. IEEE Asian Test Symp., pp. 325-330 (2001).
Konemann et al., “Built-In Logic Block Observation Technique,”Proc. ITC, pp. 37-41 (1979).
Krishna et al., “3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme,”Proc. VLSI Test Symp., pp. 79-86 (2004).
Lumetta et al., “X-codes: Error control with unknowable inputs,”Proc. Int. Symp. Inform. Theory, p. 102 (2003).
Mitra et al., “X-Compact: An Efficient Response Compaction Technique,”IEEE Trans. CAD, vol. 23, Issue 3, pp. 421-432 (Mar. 2004).
Patel et al., “Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns,”Proc. VLSI Test Symp., pp. 107-112 (2003).
Pouya et al., “Synthesis of Zero-Aliasing Space Elementary-Tree Space Compactors,”Proc. VLSI Test Symp., pp. 70-77 (1998).
Rajski et al., “Convolutional Compaction of Test Responses,”Proc. ITC, pp. 745-754 (2003).
Rajski et al., “Embedded Deterministic Test for Low Cost Manufacturing Test,”Proc. ITC, pp. 301-310 (2002).
Saluja et al., “Testing Computer Hardware Through Data Compression in Space and Time,”Proc. ITC, pp. 83-89 (1983).
Sharma et al., “X-filter: Filtering unknowns from compacted test responses,”Proc. ITC, 9 pp. (Nov. 8, 2005).
Sinanoglu et al., “Efficient Construction of Aliasing-Free Compaction Circuitry,”IEEE Micro, vol. 22, Issue 5, pp. 82-92 (Sep.-Oct. 2002).
Sinanoglu et al., “Parity-Based Output Compaction for Core-Based SOCs,”Proc. European Test Workshop, pp. 15-20 (2003).
Volkerink et al., “Packet-based Input Test Data Compression Techniques,”Proc. ITC, pp. 154-163 (2002).
Wang et al., “On Compacting Test Response Data Containing Unknown Values,”Proc. Trans. CAD, pp. 855-862 (2003).
Wohl et al., “Analysis and Design of Optimal Combinational Compactors,”Proc. VLSI Test Symp., pp. 101-106 (2003).
Wohl et al., “Efficient Compression and Application of Deterministic Patterns in a Logic BIST Architecture,”Proc. Design Automation Conf., pp. 566-569 (2003).
Wohl et al., “Scalable Selector Architecture for X-Tolerant Deterministic BIST,”Proc. Design Automation Conf., pp. 934-939 (2004).

Affiliated with

Also associated with

Rating

Removing the effects of unknown test values from compacted... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Removing the effects of unknown test values from compacted..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Removing the effects of unknown test values from compacted... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2806639