Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-11-14
2006-11-14
Baumeister, Bradley (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S778000, C438S780000, C438S782000, C438S631000, C257SE21257, C257SE21259, C257SE21261
Reexamination Certificate
active
07135398
ABSTRACT:
An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.
REFERENCES:
patent: 6159842 (2000-12-01), Chang et al.
patent: 6187663 (2001-02-01), Yu et al.
patent: 6245662 (2001-06-01), Naik et al.
patent: 6265779 (2001-07-01), Grill et al.
patent: 6265780 (2001-07-01), Yew et al.
patent: 6358842 (2002-03-01), Zhou et al.
patent: 6362091 (2002-03-01), Andideh et al.
patent: 6380091 (2002-04-01), Wang et al.
patent: 6383920 (2002-05-01), Wang et al.
patent: 6391757 (2002-05-01), Huang et al.
patent: 6395632 (2002-05-01), Farrar
patent: 6406994 (2002-06-01), Ang et al.
patent: 6437443 (2002-08-01), Grill et al.
patent: 6451712 (2002-09-01), Dalton et al.
patent: 6472306 (2002-10-01), Lee et al.
patent: 6486557 (2002-11-01), Davis et al.
patent: 6573604 (2003-06-01), Kajita
patent: 6624053 (2003-09-01), Passemard
patent: 6677231 (2004-01-01), Tsai et al.
patent: 6764774 (2004-07-01), Grill et al.
patent: 6798043 (2004-09-01), Steiner et al.
patent: 6828229 (2004-12-01), Lee et al.
patent: 6867125 (2005-03-01), Kloster et al.
patent: 6879046 (2005-04-01), Gibson et al.
patent: 7023093 (2006-04-01), Canaperi et al.
patent: 2002/0024150 (2002-02-01), Farrar
patent: 2002/0048929 (2002-04-01), Naik et al.
patent: 2002/0048931 (2002-04-01), Farrar
patent: 2002/0052125 (2002-05-01), Shaffer, II et al.
patent: 2002/0117737 (2002-08-01), Gates et al.
patent: 2002/0117754 (2002-08-01), Gates et al.
patent: 2002/0117760 (2002-08-01), Gates et al.
patent: 2002/0130416 (2002-09-01), Wang et al.
patent: 2002/0130417 (2002-09-01), Yew et al.
patent: 2002/0137323 (2002-09-01), Loboda
patent: 2002/0164865 (2002-11-01), Furusawa et al.
patent: 2002/0164889 (2002-11-01), Tsai et al.
patent: 2003/0001273 (2003-01-01), Steiner et al.
patent: 2003/0089988 (2003-05-01), Matsuura
patent: 2003/0134499 (2003-07-01), Chen et al.
patent: 2003/0176058 (2003-09-01), Weidman et al.
patent: 2003/0183939 (2003-10-01), Kakamu et al.
Hongring Yang et al.: Multilevel Damascene Interconnection in Integration of MOCVD Cu and Low-k Fluorinated Amorphous Carbon; Proceedings of the Symposium on Low-Dielectric constant Materials V, San Francisco, Apr. 5-8, 1999; Mat. Res. Soc. Symp. Proc. 565, p. 129-134, XP008035921.
M. Tada et al., “Copper Dual Damascene Interconnects in Porous Organosilica Film with Organic Hard-mask and Etch-Stop Layers For 70nm-Node ULSIs” Proc. IEEE Int. Interconnect Conference 2002 Burlingame USA May 3-6, 2002 pp. 12-14.
Hasegawa T, et al. “Copper Dual Damascene Interconnects with Low-K (KOFF 3.0) Dielectrics Using Flaretm and an Organo-Silicate Hard Mask” International Electron Devices Meeting 1999 IEDM. Technical Digest. Washington DC, Dec. 5-8, 1999 New York, NY IEEE US, Aug. 1, 2000 pp. 623-626.
T. Usami, et al. “Stopper-less Hybrid Low-K/Cu DD Structure Fabrication Combined with Low-K CMP” Proc. IEEE Int. Interconnect Conf. 2002, burligame USA May 3-5, 2002 pp. 250-252.
“Robust 130nm-Node Cu Dual Damascene Technology with Low-K Barrier SiCN”, H, Aoki, K. Torii, T. Oshima, J.Noguchi, U. Tanaka, H. Yamaguchi, T. Saito, N. Miura, T. Tamaru, N. Konishi, S. Uno, S. Morita, T. Fujii, and K. Hinode,Device Development Center Hitachi, Ltd. 2001 IEEE, 76-IEDM 01.
“A. 0.11 CMOS Technology with Copper and Very-low-K Interconnects for High Performance System-On-A-Chip Cores”Y. Takao, H. Kudo, J. Mitani, Y. Kotani, S. Yamagushi, K. Yoshie, and M. Kawano, Manufacturing TechnologyDevelopment Division, Fujitsu Limited; 2000 IEEE, IEDM 00-559.
“A High Performance 0.13 um Copper DEOL Technology with Low-K Dielectric” R.D. Goldblatt, B. Agarwala, M.B. Anand, E.P. Barth, G.A. Biery, Z.G. Chen, S. Cohen, J.B. Connolly, A. Cowley, T. Dalton, S.K. Das, C.R. Davis, A. Deutsch, C. DeWan, D.C. Edelstein, P.A. Emmi, C.G. Faltermeir, J.A. Fitzsimmons, J. Hedrick, J.E. Heidenreich, C.K. Hu, J.P. Hummel, P. Jones, E. Kaltalioglu, B.E. Kastenmeier, M. Krishnan, W.F. Landers, E. Liniger, J. Kiu, N.E. Lustig, S. Malhotra, D.K. Manger, V. McGahay, R. Mih, H.A. Nye, S. Purushothaman, H.A. Rathore, S.C. Seo, T. M. Shaw, A. H. Simon, T.A. Spooner, M. Stetter, R.A. Wachnik, J. G. Ryan, IBM Semiconductor Research and Development Center and Infineon Technologies, Inc. 2000 IEEE.
Angyal Matthew S.
Biery Glenn A.
Fitzsimmons John A.
Gates Stephen M.
Greco Stephen E.
Anya Igwe U.
Baumeister Bradley
Jaklitsch Lisa U.
LandOfFree
Reliable low-k interconnect structure with hybrid dielectric does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reliable low-k interconnect structure with hybrid dielectric, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reliable low-k interconnect structure with hybrid dielectric will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3624279