Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-14
2003-09-23
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S642000, C438S652000, C438S653000, C438S675000, C438S687000
Reexamination Certificate
active
06624066
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of fabricating liners/barriers in contacts, vias, and copper interconnects in semiconductor devices and more specifically to the elimination of overhang in liner/barrier/seed deposition using sputter etch.
BACKGROUND OF THE INVENTION
As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a conventional interconnect process, the aluminum (and any liner/barrier metals) are deposited, patterned, and etched to form the interconnect lines. Then, an interlevel dielectric (ILD) is deposited and planarized. In a damascene process, the ILD is formed first. The ILD is then patterned and etched. A thin liner/barrier material is then deposited over the structure followed by copper deposition over the liner/barrier material. Then, the copper and liner/barrier material are chemically-mechanically polished to remove the material from over the ILD, leaving metal interconnect lines. A metal etch is thereby avoided.
The most practical technique for forming copper interconnects is electrochemical deposition (ECD). In this process, after the liner/barrier material is deposited, a seed layer of copper is deposited. Then, ECD is used to deposit copper over the seed layer. Unfortunately, physical vapor deposition (PVD) processes typically used to deposit the liner/barrier and seed materials have poor step coverage. This is due to the fact that PVD processes use a line of sight technique. As a result, an overhang
18
of liner/barrier
14
and/or seed
16
material occurs at the top of a trench or via
12
as illustrated in FIG.
1
. The overhang causes a severe problem during the subsequent copper ECD. Specifically, a seam occurs in the copper fill material.
One proposed solution for overcoming the above problem uses a pre-sputter etch after the trench and via or contact etch, but before liner/barrier deposition. Unfortunately, the sputter etch step can deposit copper onto the sidewalls. Copper can then diffuse through the dielectric and cause reliability problems.
SUMMARY OF THE INVENTION
The invention uses a two layer barrier for a via or contact. A thin CVD barrier is deposited over a structure including within a via or contact hole. A sputter etch is then performed to remove the CVD barrier at the bottom of the via/contact. A second barrier is deposited after the sputter etch. A metal fill process can then be performed.
An advantage of the invention is providing an improved interconnect process having low via/contact resistance and improved reliability.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.
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patent: 5985762 (1999-11-01), Luce
patent: 6156648 (2000-12-01), Huang
patent: 6177347 (2001-01-01), Liu
patent: 6211069 (2001-04-01), Hu et al.
patent: 6284657 (2001-09-01), Chooi et al.
patent: 6287977 (2001-09-01), Hashim et al.
patent: 6335570 (2002-01-01), Mori et al.
patent: 6380065 (2002-04-01), Komai et al.
patent: 6380082 (2002-04-01), Huang et al.
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patent: 2000-323571 (2000-11-01), None
Taguchi (JP 200-323571) (Translation).
Lin Ching-Te
Lu Jiong-Ping
Brady III W. James
Garner Jacqueline J.
Guerrero Maria
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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