RELACS process to double the frequency or pitch of small...

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate

Reexamination Certificate

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C438S780000

Reexamination Certificate

active

06383952

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to forming small critical dimension patterns on a layer by using a RELACS polymer. In particular, this invention relates to forming small patterns by forming a RELACS polymer around a photoresist, removing portions of the RELACS polymer, and then removing the photoresist, to thereby form the small patterns by use of the remaining RELACS polymer.
2. Description of the Related Art
As critical dimensions (CD) in semiconductor device fabrication get smaller and smaller, so too do the dimensions for forming patterns, such as separate poly-gates, on a semiconductor substrate. For example, obtaining poly-gates having a CD (e.g., width) of 100 nanometers or less, will soon be required for forming semiconductor devices.
Conventional photolithography techniques for forming small CD poly-gates are reaching limitations due to the small CD required for current semiconductor device fabrication. Conventionally, a photoresist (in this case, a positive photoresist) is provided on a substrate, and then a particular pattern is formed by exposing certain portions of the photoresist using a mask. The exposed portions of the photoresist are then removed by subjecting the photoresist to a developer solution, thereby rendering the exposed portions of the photoresist soluble.
The patterned photoresist is then used as a hard mask, in order to form patterns, such as one or more poly-gates. The problem with this technique is that the masks required for forming very small poly-gates may have inaccuracies due in part to light diffraction problems (e.g., Rayleigh diffraction limit), focus problems, and the small CDs required for forming the very small patterns.
Therefore, a better technique for forming very small patterns is desired.
SUMMARY OF THE INVENTION
According to an embodiment of the invention, there is provided a method for doubling the pitch of a given feature and simultaneously forming small patterns on a semiconductor substrate. The method includes a step of forming a photoresist layer on the substrate. The method also includes a step of patterning the photoresist layer. The method further includes a step of spreading a RELACS polymer on the patterned photoresist layer. The method also includes the step of polishing or etching back a portion of the RELACS polymer, to leave the RELACS polymer only on sidewalls of each patterned portion of the patterned photoresist layer. The method still further includes the step of removing the patterned photoresist layer, whereby the RELACS polymer on is the sidewalls remain, to thereby form a polysilicon pattern on the substrate.


REFERENCES:
patent: 6033952 (2000-03-01), Yasumura et al.
L.J. Peters, “Resist Join the Sub-&lgr; Revolution”, Semiconductor International, 1999, pp. 1-7 Cahners Business Information, A Division of Reed Elsevier, Inc.
T. Toyoshima et al., “0.1 &mgr;m Level Contact Hole Pattern formation with KrF Lithography by Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS)”, IEEE, pp. 12.5.1-12.5.4, 1998 Advanced Technology R&D Ctr., Mitsubishi Electric Corp.

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