Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-06-26
2003-04-01
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700
Reexamination Certificate
active
06542418
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to redundant arrays of a semiconductor memory array and more particularly to an improved redundant array, the elements of which can be used as either replacement bitlines or replacement wordlines.
2. Description of the Related Art
Semiconductor memory arrays often include redundant repair elements to improve product yield, especially when fabricating a product in a new technology or when a product design point is completely new. These redundant repair elements may be included as either additional wordlines and bitlines in the primary array or as an entirely separate redundant array. Separate redundant arrays consist of multiple bitline and wordline repair elements.
FIG. 1
illustrates the use of redundant wordlines
11
and bitlines
12
in the primary array
13
.
FIG. 2
illustrates the use of redundant wordline
20
and bitline
21
elements in a separate redundant array
22
. Each repair element, whether incorporated into the primary array
13
or separated into a redundant array
22
, can be mapped into the decode and data paths
14
,
15
of the primary memory array
13
to replace faulty memory cells in the primary array. When a separate redundant array
22
is mapped into the decode paths of the primary array, the data from the redundant array is multiplexed with the data from the primary array with mux
23
. This provides substantial performance benefits to large memory arrays (see U.S. Pat. No. 5,793,683, which is incorporated herein by reference). Thus, separate redundant array techniques are the focus of this disclosure.
Conventional systems use repair elements that are predesignated for a single use, either a bitline repair element that replaces a single bitline (a grouping of cells common to a single sense-amplifier) in the primary array or a wordline repair element that replaces a single wordline (a grouping of cells with a common word line driver) in the primary array. These bitline and wordline repair elements exclusively replace either faulty bitlines or wordlines, respectively, in the primary array. Conventional systems also can include bitline repair elements that can replace multiple bitlines and word line elements which can replace multiple word lines. For the purposes of this disclosure, these conventional redundancy repair systems are referred to as having “single-use redundancy.”
One problem with single-use redundancy is that each repair element is restricted in its use to the replacement of either a faulty bitline or a faulty wordline according to its predesignated function. This restriction limits the usefulness of each repair element in the redundant array. A redundant memory array might have a total of eight repair elements as in
FIG. 2
, where four of those elements are bitline repair elements
24
and the other four elements are wordline repair elements
25
. Although the redundant array contains a total of eight repair elements, only four faulty bitlines and four faulty wordlines may be repaired. If the number of defective bitlines or wordlines exceeds
4
, the array would not be able to be repaired and would have to be scrapped. The invention described allows each repair element in the redundant array to be used as either a bitline repair element or a wordline repair element. Using the invention, a redundant array containing eight repair elements can repair eight faulty bitlines or eight faulty wordlines, or any combination thereof up to a maximum of eight total repairs.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional redundant memory arrays the present invention has been devised, and it is an object of the present invention to provide a structure and method for an improved redundant memory array that includes elements that can be used as either wordlines or bitlines.
In order to attain the object(s) suggested above, there is provided, according to one aspect of the invention, an integrated circuit memory structure that includes a main array of memory elements having wordlines and bitlines and a redundant array of redundant memory elements external to and connected to the main array. Each of the redundant memory elements can replace either one of the wordlines or one of the bitlines. The wordlines and the bitlines are the same size and the redundant memory elements are the same size as the wordlines and the bitlines.
The invention compares logic and corresponding fuses for identifying which one of the wordlines or the bitlines is replaced by each of the redundant memory elements. The fuses include two master fuses that identify whether each of the redundant memory elements replaces one of the bitlines or one of the wordlines. The invention includes at least one multiplexor/decoder for decoding a memory address to a corresponding address within the redundant memory array. The invention further includes a multiplexor for selectively connecting a data line to either the main array or the redundant array.
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patent: 5469390 (1995-11-01), Sasaki et al.
patent: 5671184 (1997-09-01), Meyer
patent: 5708613 (1998-01-01), Creed et al.
patent: 5793683 (1998-08-01), Evans
patent: 5963489 (1999-10-01), Kirihata et al.
patent: 5991211 (1999-11-01), Kato et al.
patent: 6011735 (2000-01-01), Ooishi et al.
patent: 6011742 (2000-01-01), Zheng
patent: 6018811 (2000-01-01), Merritt
patent: 6038179 (2000-03-01), Eustis et al.
Braceras George M.
Hansen Patrick R.
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