Redundancy circuit of a semiconductor memory device

Details Redundancy circuit of a semiconductor memory device Redundancy circuit of a semiconductor memory device

1995-06-30

1996-11-19

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 3652257, G11C 700

Patent

active

055769993

ABSTRACT:
A redundancy circuit of the semiconductor memory device having a normal memory cell array for storing data, a redundant memory cell for repairing the fail cells in the normal memory, cell array, a normal decoder for receiving addresses and designating the normal memory cell, a redundancy decoder for selecting the redundant memory cell. The circuit includes a control part which is controlled by a control clock and has fuses for programming fail addresses of the addresses, to be applied, a transmission part which is controlled by an output signal of the control part and has a first path for outputting addresses in-phase with the addresses and a second path for outputting addresses out of phase with the addresses, thereby selecting the first path before repair to select both the normal memory cell and redundant memory cell by the normal and redundancy decoders, and cutting off the fuses corresponding to the fail addresses and selecting the second path during the repair to select the redundant memory cell by the redundancy decoder, thus enabling burn-in of both the normal memory cell and redundant memory cell during the burn-in test.

REFERENCES:
patent: 5060197 (1991-10-01), Park et al.
patent: 5297088 (1994-03-01), Yamaguchi
patent: 5383156 (1995-01-01), Komatsu

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