Redundancy circuit for memory devices having high frequency addr

Details Redundancy circuit for memory devices having high frequency addr Redundancy circuit for memory devices having high frequency addr

1996-12-13

1999-01-19

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, G11C 700

Patent

active

058620877

ABSTRACT:
A redundancy circuit for activating redundant memory cells when a semiconductor memory device is found to have defective memory cells, which redundancy circuit comprises, in order to overcome the problems of an address reset and a precharging of the first node which determines the redundancy addressing output signal of the redundancy circuit, additional switching circuit which is controlled by a clock signal of the memory device being made to be connected between a ground node and a switching circuit connected to a plurality of fuses, and a precharging circuit for precharging the first node to a high voltage level being made to also controlled by the clock signal.

REFERENCES:
patent: 5058059 (1991-10-01), Matsuo et al.
patent: 5495446 (1996-02-01), Teel et al.
patent: 5574689 (1996-11-01), Morgan
patent: 5590085 (1996-12-01), Yuh et al.
patent: 5677882 (1997-10-01), Isa et al.

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