Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2000-05-17
2002-12-24
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S721000, C714S710000, C714S718000
Reexamination Certificate
active
06499118
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to automatic test equipment and more particularly a method and apparatus for carrying out an optimal redundancy analysis on a multi-tester system.
BACKGROUND OF THE INVENTION
Semiconductor memory manufacturers employ a variety of processes to fabricate memory devices or “chips.” Each process attempts to optimize the requirements for high yields and high throughput in order for the manufacturer to remain competitive.
One of the more critical processes involves automated testing of each chip at the wafer level with automatic test equipment. The testing, among other things, generally involves reading data to and writing data from each chip according to pre-programmed test patterns, and detecting the addresses of failed memory cells.
To optimize yields in the test process, memory chips typically include spare rows and columns that can be implemented to replace faulty rows and/or columns detected in the device by the test equipment. Since only a limited number of spares are available to repair the chip, the tester generally determines a “solution”, or arrangement where a minimum number of spares can repair a maximum number of failed cells in order to bring the device within acceptable tolerances. One significant method for generating such a solution is found in U.S. Pat. No. 5,795,797, hereby expressly incorporated by reference herein, and assigned to the assignee of the present invention.
Recently, chip makers have recognized the need to test wafers in different environments, such as under high and low temperatures. This is because those skilled in the art have found that failures may occur at some addresses in a particular portion of the memory array, while different failures may occur in the same portion of the array at low temperature.
Conventionally, testing wafers at different temperatures involves employing two separate testers—one for high temperature testing, and the other for low temperature testing. The wafer is first tested at high temperature, and the failure data processed to determine a high temperature solution for the available spare rows and/or columns.
FIG. 2
illustrates the high temperature solution whereby spare columns C
1
, C
2
and C
3
, and spare rows R
1
and R
2
repair the memory array
30
.
The solution, represented electronically by far less data than the first fail data set, is then transferred to the low temperature tester, where the wafer is re-tested. The fails detected from the low temperature tester are then analyzed and a solution is determined with respect to any remaining spares not already allocated by the first solution. As further shown in
FIG. 2
with the same memory array
30
, two additional fails in the same column were detected at low temperature. However, because all of the column spares are allocated, with only one spare row remaining, the fail at
35
cannot be repaired. As a result, the chip would most likely fail testing, thereby contributing to a decrease in the yield of acceptable devices on the wafer.
While the conventional multi-tester method of carrying out a redundancy analysis is beneficial for its intended applications, it does not always provide the optimal solution. This is most likely due to the undesirability of transferring the large amount of bit-image data representing the high temperature fails to the low temperature tester. For conventional testers, transferring such large amounts of data to a second tester takes too much time, thereby reducing throughput.
What is needed and heretofore unavailable is a method and apparatus for carrying out a highly optimized redundancy analysis that maximizes yields while simultaneously maintaining high throughput through a multi-tester testing system. The method and apparatus of the present invention satisfies these needs.
SUMMARY OF THE INVENTION
The redundancy analysis method of the present invention provides a highly optimized way of determining a multi-tester redundancy solution without sacrificing wafer throughput. This minimizes costs associated with the test process to help a semiconductor manufacturer remain competitive.
To realize the foregoing advantages, the invention in one form comprises a method of determining a redundancy solution for a semiconductor device under test (DUT) having redundant rows and columns. The method includes the steps of first testing the DUT in a first environment with a first tester to generate a first fail data set. The first fail data set is then transferred to a second tester where the DUT is test in a second environment to generate a second fail data set. The first and second failure data sets are then merged to create a merged fail data set. A highly optimized redundancy solution is then determined based on the merged fail data set.
In another form, the invention is implemented in a process for manufacturing a semiconductor memory (DUT) organized into rows and columns of memory cells. The invention comprises a method of replacing faulty memory cells with redundant rows and columns. The method includes the steps of first selecting rows or columns to replace with redundant elements according to the steps of first testing the DUT in a first environment with a first tester to generate a first fail data set. The first fail data set is then transferred to a second tester where the DUT is test in a second environment to generate a second fail data set. The first and second failure data sets are then merged to create a merged fail data set. A highly optimized redundancy solution is then determined based on the merged fail data set. After the solution is determined, the redundant rows or columns selected in the selecting step are allocated to replace the selected rows and/or columns.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5235271 (1993-08-01), Kira
patent: 5522038 (1996-05-01), Lindsay et al.
patent: 5588115 (1996-12-01), Augarten
patent: 5754556 (1998-05-01), Ramseyer et al.
patent: 5764650 (1998-06-01), Debenham
patent: 5795797 (1998-08-01), Chester et al.
patent: 5862088 (1999-01-01), Takemoto et al.
patent: 6288955 (2001-09-01), Shibano et al.
patent: 6349240 (2002-02-01), Ogawa et al.
patent: WO 98/06103 (1998-02-01), None
Kreisman Lance
Teradyne, Inc.
Ton David
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