4. Static information storage and retrieval
  5. Read/write circuit
  6. Testing

William D. Schwarz

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Built-in redundancy analysis for memories with row and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Built-in self repair circuit with pause for data retention...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate

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Redundancy analysis for embedded memories with built-in self tes

Static information storage and retrieval – Read/write circuit – Testing
Patent

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Profile ID: LFUS-PAI-P-1703900

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