Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
1997-12-31
2001-01-16
Heckler, Thomas M. (Department: 2787)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S500000
Reexamination Certificate
active
06175928
ABSTRACT:
BACKGROUND
The invention relates to reducing timing variance of signals from an electronic device.
Electronic devices generate signal outputs that are typically triggered off a triggering event, e.g., an edge of a clock. Several factors can affect the time delay between the triggering event and the generation of the desired output. Such factors include temperature, voltage, and manufacturing process variations. Signal drivers generally operate faster at higher voltages and lower temperatures, and are generally slower at lower voltages and higher temperatures. Variations in the manufacturing process of these electronic devices, such as shifts in threshold voltages of transistors and other process conditions, can also affect the switching speeds of the transistors. Such variations in voltages, temperatures, and process can result in large variances in the device output behavior.
For example, in clocked integrated circuit (IC) devices such as microprocessors, microcontrollers, and synchronous memories, one signal timing parameter is Tco (clock to output valid), which specifies the delay from the leading edge of a clock to when the output buffers of the clocked device switch. The Tco parameter is specified in terms of Tco_min and Tco_max, with Tco_min specifying the fastest time from clock to output valid and Tco_max indicating the slowest time from clock to output valid.
The variance in the delay time is caused by 1) the difference in flight time through circuitry in the IC device from the triggering event to the output between fast and slow conditions because circuitry tends to respond quicker in fast conditions; and 2) the difference in driver strength between fast and slow conditions (the driver output slew rate is smaller under fast conditions).
SUMMARY
The invention in one aspect is generally directed to reducing the variance in time delay between a triggering event and a desired output of an electronic device under different conditions. In another aspect, the invention is generally directed to sensing characteristics of the device using an oscillator having a frequency that is sensitive to the device characteristics.
In one aspect, the invention features an electronic device generating an output signal that changes state. The device includes a sensor to detect a characteristic of the device and a timing controller responsive to the sensor and a triggering event to control when the output signal changes state. The timing controller is configured to adjust a time delay between the triggering event and when the output signal switches state based on the characteristic detected by the sensor.
In another aspect, the invention features a method of controlling a time delay between a triggering event and switching of an output of a device. The method includes sensing a characteristic of the device. The time delay is adjusted based on the sensed characteristic.
In another aspect, the invention features a sensor for use in an electronic device. The sensor includes an oscillator having a frequency dependent upon a characteristic of the device and a count circuit responsive to the oscillator frequency to provide a value representing the characteristic of the device.
In another aspect, the invention features a circuit for determining if more than a predetermined number of data output bits are switching. The circuit includes a sensor receiving the data output bits, each data output bit capable of being at the first state or a second state. The sensor has a state that is controlled by the data output bits being at the first and second states. A comparator is configured to detect a sensor state corresponding to more than the predetermined number of the data output bits being at the first state and to output an indication that more than the predetermined number of data output bits are switching.
Other features and advantages will become apparent from the features and from the claims.
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Allen Michael J.
Conary James W.
DiMarco David P.
Liu Jonathan H.
Miller Jeffrey L.
Heckler Thomas M.
Intel Corporation
Trop Pruner & Hu P.C.
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