Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-12-12
2006-12-12
Pham, Thanhha S. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000
Reexamination Certificate
active
07148099
ABSTRACT:
In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.
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patent: 6750502 (2004-06-01), Sandhu et al.
patent: 2001/0023120 (2001-09-01), Tsunashima et al.
patent: 2004/0029321 (2004-02-01), Ang et al.
patent: 2005/0245036 (2005-11-01), Daata et al.
Nihar Mohapatra, “The Effect of High-k Gate dielectrics on Deep Submicrometer CMOS Device and Circuit Performance”, IEEE Transaction on Electronic Devices, vol. 49, No. 5, May 2002, pp. 826-831.
Brask Justin K.
Chau Robert S.
Datta Suman
Doczy Mark L.
Kavalieros Jack
Intel Corporation
Pham Thanhha S.
Trop Pruner & Hu P.C.
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