Reducing resistance in source and drain regions of FinFETs

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S349000

Reexamination Certificate

active

07939889

ABSTRACT:
A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.

REFERENCES:
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6706571 (2004-03-01), Yu et al.
patent: 6858478 (2005-02-01), Chau et al.
patent: 6905622 (2005-06-01), Padhi et al.
patent: 7190050 (2007-03-01), King et al.
patent: 7247887 (2007-07-01), King et al.
patent: 7265008 (2007-09-01), King et al.
patent: 7508031 (2009-03-01), Liu et al.
patent: 7514325 (2009-04-01), Kim et al.
patent: 7528465 (2009-05-01), King et al.
patent: 7605449 (2009-10-01), Liu et al.
patent: 2005/0153490 (2005-07-01), Yoon et al.
patent: 2005/0156202 (2005-07-01), Rhee et al.
patent: 2005/0173768 (2005-08-01), Lee et al.
patent: 2007/0120156 (2007-05-01), Liu et al.
patent: 2007/0122953 (2007-05-01), Liu et al.
patent: 2007/0122954 (2007-05-01), Liu et al.
patent: 2007/0128782 (2007-06-01), Liu et al.
patent: 2007/0132053 (2007-06-01), King et al.
patent: 2007/0235818 (2007-10-01), Anderson et al.
patent: 2007/0235819 (2007-10-01), Yagishita
patent: 2008/0265321 (2008-10-01), Yu et al.
patent: 2008/0290470 (2008-11-01), King et al.
patent: 2008/0296632 (2008-12-01), Moroz et al.
patent: 2009/0181477 (2009-07-01), King et al.
Lee, Y.-P., et al., “Selective Copper Metallization by Electrochemical Contact Displacement with Amorphous Silicon Film,” Electrochemical and Solid-State Letters, vol. 4, No. 7, 2001, pp. C47-C49, Electrochemical Society.
Magagnin, L., et al., “Gold Deposition by Galvanic Displacement on Semiconductor Surfaces: Effect of Substrate on Adhesion,” J. Phys. Chem. B, vol. 106, No. 2, 2002, pp. 401-407, American Chemical Society.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Reducing resistance in source and drain regions of FinFETs does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reducing resistance in source and drain regions of FinFETs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reducing resistance in source and drain regions of FinFETs will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2704044

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.