Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-28
2002-10-29
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S376000, C257S387000
Reexamination Certificate
active
06472715
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit structures. More particularly this invention relates to an integrated circuit structure having reduced soft error rate.
2. Description of the Related Art
As integrated circuit structures reduce down to sub 0.25 &mgr;m linewidths and the supply voltage (operating voltage) is reduced to less than ~2 volts, memory/logic devices are more prone to alpha particle-induced soft errors. The smaller the device size and the lower the supply voltage, the smaller the critical charge (Qcrit) will be for the device, where the critical charge (Qcrit) is the largest charge which can be injected into a memory array storage cell without changing the cell's logic state. Reduction of the soft error rate (SER) is, therefore, becoming more important as the memory device size shrinks and operating voltages are reduced.
The problem of alpha particle collisions is of particular concern with regard to N-channel transistors formed in P wells because of the higher mobility of electrons in silicon compared to holes, i.e, the electron in the electron-hole pair generated by the alpha particle collision is more likely to reach the N+ diffusion regions of the N channel transistor than is the corresponding hole to reach the P+ diffusion regions of a P channel transistor. Furthermore, in view of this greater sensitivity of N channel transistors to the problem of alpha particle collisions, the problem is further exacerbated for memory cells because of the preference for using N channel transistors in memory cells due to their faster speed.
FIG. 1
shows a cross-section of a typical SRAM containing both N channel and P channel transistors. A first N well
8
, a P well
10
, and a second N well
12
are shown formed in a silicon semiconductor substrate
2
. A first P channel transistor
20
formed in the surface of first N well
8
comprises P+ source/drain regions
22
and
24
separated by a gate electrode
26
formed over a channel region in first N well
8
. Separated from P channel transistor
20
by field oxide portions
6
is an N channel transistor
30
formed in the surface of P well
10
comprising N+ source/drain regions
32
and
34
separated by a gate electrode
36
formed over a channel region in P well
10
. A second P channel transistor
40
formed in the surface of second N well
12
and separated from N channel transistor
30
by field oxide
6
comprises P+ source/drain regions
42
and
44
separated by a gate electrode
46
formed over a channel region in second N well
12
.
The path or trajectory of an alpha-particle is shown passing through transistor
40
and substrate
2
at A in
FIG. 1
, with electron-hole pairs shown generated by collisions between the alpha-particle and the silicon atoms of the substrate. If sufficient electrons generated by these collisions migrate to the N+ source/drain diffusion regions
32
and
34
of N channel transistor
30
, the accumulated charge on the N+ regions
32
and
34
can cause an erroneous reading of the charge state (off/on state) of the SRAM cell, i.e., cause a soft error to occur.
In DRAM structures in the past, reduction in the soft error rate has been achieved in several ways. Y. Matsuda et al. et al., in “MeV-Boron Implanted Buried Barrier for Soft Error Reduction in Megabit DRAM”, published in Extended Abstracts of the 19th Conference on Solid State Devices and Materials, Tokyo, (1987) at pages 23-26, describe the use of a buried layer of implanted boron in a P
−
substrate to reduce the soft error rate in a DRAM cell.
More recently, T. Yamashita et al., in “Substrate Engineering for Reduction of Alpha-Particle-Induced Charge Collection Efficiency”, published in the Japan Journal of Applied Physics, at Volume 35, Part 1, No. 2B (1996) at pages 869-873, identified three schemes for reducing charge collection efficiency (by the N+ diffusion regions of the DRAM memory cell). They state that charge collection efficiency (CCE) may be reduced by preventing minority carriers from traveling toward the diffusion layer; or by absorbing minority carriers by an extra fabricated layer; or by killing minority carriers before they reach the diffusion layer.
They then describe several structures which have been used for carrying out the above schemes to attain soft error reduction in DRAM memory cells, including a retrograde P well structure, a double well construction with an N well formed below the P well in a P
−
substrate, a P well in a P
−
epitaxial layer grown on a P+ substrate, and a buried defect layer formed below a P well. The buried defect layer is formed by high dosage implant of high energy silicon or boron ions into the substrate.
With respect to the double well construction, Yamashita et al. state that the CCE for the double well construction is much lower than that of the simple retrograde well. They then note that the alpha-particle-induced electrons coming from deep inside the substrate are not collected in the diffusion layer but accumulate in the bottom n-layer of the double well construction, indicating that the bottom n-layer is found to act as an effective shield for minority carriers, even in the case of high-level injection such as the incidence of alpha-particles. They then further observe that the CCE for the double well construction of 2 &mgr;m depth is lower than that of the double well of 3 &mgr;m depth, and state that it is, therefore, considered to be more effective to put this absorptive bottom n-layer near the surface for reduction in soft error rate.
With respect to the buried defect layer, Yamashita et al. after stating that the CCE for the P well with a buried layer is much lower than that for a simple P well, observe that the lattice defects induced by the implantation are considered to play an important role since silicon implantation, which does not give rise to a potential difference in the substrate, as well as boron implantation, both reduce CCE. They then indicate that these defects are considered to act as minority carrier killers.
Yamashita et al. then conclude that CCE for the double well is low because the bottom n-layer acts as an effective absorber for minority carriers, and that the CCE for a P well with a heavily doped buried layer fabricated by high-energy and high-dosage ion implantation is as low as that for a double well because the carrier lifetime is short in the buried layer due to lattice defects, and that it is more effective to fabricate the bottom n-layer or the buried layer near the surface to reduce CCE.
While the foregoing structures solved or at least mitigated the problem of alpha-particle-induced soft errors in DRAMS, similar soft error rate (SER) problems induced by alpha-particle radiation were not noted in at least some of the SRAM structures until recently in connection with the scaling down to the sub-0.25 &mgr;m regime. In view of such prior art teachings concerning the use of a buried defect layer to solve SER problems in DRAMs, this buried layer approach was experimented with in SRAM structures. Quite surprisingly, the addition of a buried defect layer beneath the P well of an SRAM structure was found to have little if any benefit in reducing SER.
Upon further consideration and comparison of the conventional prior art DRAM construction, it was concluded that the reason why the addition of a buried layer to the prior art SRAM structure did not reduce the soft error rate (unlike the prior art DRAM) may be due to the presence of both N wells and P wells in a prior art SRAM structure as shown in
FIG. 1
, compared to the single well of a prior art DRAM, which is usually a P well so that a faster N channel transistor may be constructed therein.
It was concluded that the presence of N wells in the prior art SRAM might be already providing the same amount of SER reduction in an SRAM as does the buried layer in a DRAM, thus rendering the addition of a buried layer in an SRAM construction superfluous. It was further conclud
Castagnetti Ruggero
Duan Franklin
Kong Weiran
Liu Yauh-Ching
Peterson Steven Michael
Chaudhuri Olik
Ha Nathan W.
LSI Logic Corporation
Taylor John P.
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