Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-12-18
2001-03-27
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S303000, C438S305000
Reexamination Certificate
active
06207520
ABSTRACT:
RELATED APPLICATIONS
This application is related to the co-filed and co-assigned application entitled “RAPID THERMAL ANNEAL WITH A GASEOUS DOPANT SPECIES,” now U.S. Pat. No. 6,124,175, issued Sep. 26, 2000, which is hereby incorporated by reference.
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit manufacturing and more particularly to rapid thermal anneal with a gaseous dopant species to form lightly doped regions within a semiconductor substrate.
BACKGROUND OF THE INVENTION
An insulated-gated field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located within a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
Within a transistor, each of the source and drain meets the substrate underneath the gate at what is known as a junction. In particular, in certain types of field-effect transistors (FET's), the lightly doped source and drain regions meet the substrate underneath the gate at a junction. For example, the substrate may be p-type semiconductor material, while the lightly doped regions may be doped such that they are n-type semiconductor material. The contact between the n-type semiconductor material and the p-type semiconductor material is thus called the p-n junction.
In a p-n junction, electron holes diffuse from the p-region, where their concentration is high, to the n-region, where their concentration is low. The deficit of positively charged holes creates a layer of negatively charged acceptors in the p-region close to the junction. In a similar way, electrons diffuse from the n-region, where their concentration is high, to the p-region where their concentration is low. The deficit of negatively charged electrons creates a layer of positively charged donors in the n-region near the junction.
This charged region, nearly devoid of holes in the p-region and nearly devoid of electrons in the n-region, is called a space charge region, or a depletion region. The charges in the depletion region create a potential barrier that prevents more electrons from coming into the p-region and prevents more holes coming into the n-regions. This potential barrier exists at the p-n junction without any applied bias. The potential difference is caused by different doping of the p and n regions.
Commonly, devices such as microprocessors for personal computers include a plurality of transistors. Desirably, these transistors have shallow depletion regions, or “shallow junctions.” Shallow depletion regions provide for lower potential barriers within the transistors, meaning that they may be switched on and off more quickly than transistors having higher potential barriers. Semiconductor transistors, however, typically have large or “high” depletion regions, such that their potential barriers are correspondingly high, meaning that devices in which these transistors are fabricated may not have desirable performance characteristics, especially in terms of speed (clock rate).
This undesirable performance becomes especially disadvantageous and problematic in applications where speed is of the utmost importance, such as in microprocessors. There is a need, therefore, to fabricate transistors having shallow junctions, such that their correspondingly low potential barriers result in high-performance devices incorporating the transistors.
SUMMARY OF THE INVENTION
The above-mentioned shortcomings, disadvantages and problems are addressed by the present invention, which will be understood by reading and studying the following specification. The invention relates to the rapid thermal anneal with a gaseous dopant species for formation of a shallow lightly doped region. In one embodiment, a method includes four steps. In the first step, at least one layer is applied over at least one gate over a semiconductor substrate. In the second step, an ion implantation is performed to form source and drain regions within the substrate. In the third step, the layers are removed. In the fourth step, a rapid thermal anneal with a gaseous dopant species is performed to form lightly doped regions within the substrate. Desirably, the lightly doped regions meet the substrate underneath the gate at shallow junctions. These shallow junctions allow for the fabrication of high-performance devices such as microprocessors.
In a further embodiment of the invention, where there are two gates (a first gate and a second gate), prior to the performance of the ion implantation, a first mask is deposited over the first gate. The mask is desirably an oxide mask. The rapid thermal anneal is performed with a negatively charged gaseous species, such as arsenic. After this rapid thermal anneal, the first mask is removed, and a second mask is deposited over the second gate. The second mask is also desirably oxide. A second ion implantation is performed, the at least one layer is removed from the first gate, and a second rapid thermal anneal is performed, this time with a positively charged gaseous species, such as boron. The second mask is then removed. The resulting structure thus includes a NMOSFET (the second gate with source and drain regions that are N-doped) and a PMOSFET (the first gate with source and drain regions that are P-doped).
The present invention describes methods, devices, and computerized systems of varying scope. In addition to the aspects and advantages of the present invention described here, further aspects and advantages of the invention will become apparent by reference to the drawings and by reading the detailed description that follows.
REFERENCES:
patent: 4837179 (1989-06-01), Foster et al.
patent: 5006477 (1991-04-01), Farb
patent: 5234850 (1993-08-01), Liao
patent: 5780350 (1998-07-01), Kapoor
patent: 5861335 (1999-01-01), Hause et al.
patent: 6004852 (1999-12-01), Yeh et al.
Fulford H. Jim
Gardner Mark I.
Advanced Micro Devices , Inc.
Guerrero Maria
Jr. Carl Whitehead
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