Random cache read

Details Random cache read Random cache read

2006-10-17

2006-10-17

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S230030

Reexamination Certificate

active

07123521

ABSTRACT:
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

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