Random access memory with plural simultaneously operable banks

Details Random access memory with plural simultaneously operable banks Random access memory with plural simultaneously operable banks

1997-07-11

1999-01-26

Mai, Son

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

3652303, 3652305, G11C 800

Patent

active

058645055

ABSTRACT:
In a random access memory for enabling read operations and write operations to be carried out simultaneously, the memory cell matrix either is divided into a plurality of banks, each bank including a write enable signal line, an out enable signal line, a data input/output line, a row address designation circuit, a column address designation circuit, a read/write control circuit, an input data buffer circuit, and an output data buffer circuit; or includes separate row address designation circuits for reading and writing and separate column address designation circuits for reading and writing.

REFERENCES:
patent: 4807189 (1989-02-01), Pinkham et al.
patent: 4879692 (1989-11-01), Tokushige
patent: 5200925 (1993-04-01), Morooka
patent: 5367488 (1994-11-01), An
patent: 5384745 (1995-01-01), Konishi
patent: 5539696 (1996-07-01), Patel
patent: 5544093 (1996-08-01), Ogawa
patent: 5566371 (1996-10-01), Ogawa

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