Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-06-19
2007-06-19
Wilczewski, M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S279000, C438S288000, C438S771000
Reexamination Certificate
active
11113507
ABSTRACT:
Methods are disclosed for fabricating multi-bit SONOS flash memory cells, comprising forming a first dielectric layer and a charge trapping layer over a substrate of a wafer and selectively etching the dielectric and charge trapping layers down to a substrate region to form a bitline opening, then implanting a dopant ion species into the substrate associated with the bitline opening in a bitline region. A radical oxidation process is then used to form a second dielectric layer of a triple layer dielectric-charge trapping-dielectric stack over the charge trapping layer and to fill the bitline opening in the bitline regions of the wafer. Finally, a wordline structure is then formed over the triple layer dielectric-charge trapping-dielectric stack and the bitline regions of the wafer. A multi-bit flash memory array is also disclosed, comprising a bitline region in a substrate, a first dielectric layer overlying the substrate substantially adjacent to and substantially exposing the bitline region, a charge trapping layer overlying the first dielectric layer substantially adjacent to and substantially exposing the bitline region, a bitline oxide isolation structure or layer extending continuously over the bitline region and charge trapping layer, the isolation structure comprising a single dielectric material layer formed by the radical oxidation process, and a conductive wordline overlying the bitline oxide isolation structure or layer.
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Jeon Joong
Qian Weidong
Shiraiwa Hidehiko
Advanced Micro Devices , Inc.
Eschweiler & Associates LLC
Spansion LLC
Thomas Toniae M.
Wilczewski M.
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