Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2003-03-31
2004-11-30
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C714S715000, C714S738000
Reexamination Certificate
active
06826100
ABSTRACT:
BACKGROUND
The invention is related to methodologies for testing computer systems and their integrated circuit (IC) components, during and after manufacture, to determine whether their electrical specifications have been met as well as that they have been assembled correctly.
Industry trends for high performance computer systems, such as those that use a Pentium processor and an associated chipset by Intel Corp., Santa Clara, Calif., are towards faster product cycle times (time to market) with sustained high quality. At the same time, component to component bus speeds are increasing beyond several GHz, and printed wiring board densities are increasing, to meet the need for greater performance. These demands are rendering conventional testing techniques such as oscilloscope and logic analyzer probing less reliable, or even impossible, on high speed interfaces, both in the high volume mnanufacturing setting as well as earlier in the electrical validation and verification-setting.
At the board and platform level, the system has its primary components, including the processor, system chipset, and memory, installed on a motherboard. In that stage of manufacturing, transaction-based tests have been used, in a board or platform high volume manufacturing setting, to verify a wide range of storage and logic functions of the system. Such tests evaluate whether the memory subsystem and the I/O subsystem work according to their electrical specifications. The test is performed by the processor executing a special test routine, during or after booting an operating system (OS) program, that causes test patterns that are part of the test routine to be written to and then read from addresses that span the computer system. However, faults of a high frequency type (such as due to cross talk between adjacent signal lines and inter-symbol interference (ISI) due to transmission line effects) cannot be detected or isolated using such techniques, due to the coarse test granularity and high instruction overhead associated with running an OS-based test program.
Another type of computer system test calls for the processor to execute firmware/software that operates at a lower level than an OS-based program, prior to booting the operating system. These include basic I/O system (BIOS) and extended firmware interface (EFI) programs. Although these types of tests provide relatively low-level, and hence more accurate, control of component functionality and interconnect buses, system interactions cannot be stressed to their bandwidth specifications in such tests. In addition, the ability of BIOS/EFI tests to isolate a fault with sufficient granularity is also limited.
Finally, there is a low level technique known as boundary scan testing (or the joint Test Access Group, JTAG, protocol) which calls for on-chip circuitry used to control individual bits transmitted between components. Once again, however, there is no provision for testing high frequency faults. For example, a boundary scan test may detect “opens” and “shorts” while running at a 10 MHz clock, whereas normal signaling speed on the interconnect will be in the GHz range.
The related applications identified above, which are assigned to the same assignee as that of this application, namely Intel Corp., describe an interconnect built-in self test (IBIST) methodology. That solution addresses some of the shortcomings of conventional computer system testing, e.g. isolating high-speed faults of chip to chip interconnects. As mentioned in those applications, a BIST unit, which resides in an IC component of the system and is separate in function from the core, may be provided with a control interface (e.g. JTAG; System Management Bus (SMBus)). This permits configuration and programming (e.g. via a tester external to the computer system board and platform; on-board system firmware or basic I/O system (BIOS) programming) of an IBIST test pattern. In that case, a separate, victim-aggressor test pattern may be launched by the BIST unit, to the external pins of its associated IC component, in each cycle of a test session. Using the control interface, a victim pin assignment can be changed for each cycle, by reprogramming a pattern register of the BIST unit with a different victim-aggressor pattern.
REFERENCES:
patent: 6477674 (2002-11-01), Bates et al.
patent: 6609221 (2003-08-01), Coyle et al.
U.S. patent application Ser. No. 10/393,223, Nejedlo, filed Mar. 20, 2003.
U.S. patent application Ser. No. 10/224,492, Tripp et al., filed Aug. 21, 2002.
Babcock Sean R.
Ellis David G.
Gayles Eric S.
Gollapudi Eshwar
Khan Amjad
Blakely , Sokoloff, Taylor & Zafman LLP
Dinh Son T.
Intel Corporation
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