Coating processes – Direct application of electrical – magnetic – wave – or... – Plasma
Reexamination Certificate
2001-03-28
2004-03-23
Meeks, Timothy (Department: 1762)
Coating processes
Direct application of electrical, magnetic, wave, or...
Plasma
C427S579000, C427S578000, C427S248100, C427S249150, C427S255370
Reexamination Certificate
active
06709721
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a method and apparatus for depositing a carbon doped silicon oxide layer on a substrate.
2. Background of the Related Art
One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric films on a substrate by chemical reaction of gases. Such deposition processes are generally referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed on the substrate. Plasma-enhanced CVD techniques promote excitation and/or disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone, thereby creating a plasma of highly reactive species.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 &mgr;m and even 0.18 &mgr;m feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries. Additionally, the density of devices formed on a single die has increased. As dimensions decrease, the number of die per substrate increases. Therefore, a goal in designing and fabricating these electronic devices is to maximize the usable surface area of a substrate.
In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having a low dielectric constant (k<4.0) to reduce the capacitive coupling between adjacent metal lines. An example of films having dielectric constants of about 3.0 or less are films deposited from organosilicon compounds, such as organo silanes and organo siloxanes, at conditions sufficient to deposit silicon oxide films containing from about 1% to about 50% carbon by atomic weight.
One issue with carbon doped oxides is the hardness of the film. Soft films are susceptible to damage, particularly at the substrate edge. A typical carbon doped silicon oxide film has a film hardness, in gigapascals (GPa=kg×10
9
/m sec
2
), of about 1.2 GPa to about 1.23 GPa. Films having a GPa of less than about 1.2 at the substrate edge have been known to peel during subsequent processing, such as chemical mechanical polishing (CMP).
Another issue which can effect the mechanical properties at the substrate edge is shielding, i.e., preventing deposition around the substrate edge. Typically during CVD, the edge of the substrate is shielded to prevent deposition from about 3 mm from the edge and the backside of the substrate. Backside and edge deposition may cause the substrate to adhere to the support or cause peeling and flaking of the material being deposited resulting in chamber and substrate contamination. Eventually, particulate contamination may clog holes in the showerhead that facilitates passage of precursor gases therethrough necessitating the showerhead be removed and cleaned or replaced. Particulate contamination may also damage other chamber components and substrates resulting in reduced yield, increased down time, and increased production costs. One approach to prevent backside and edge deposition is to shield the edge of the substrate with a shadow ring. Another approach is to route a purge gas through holes in the substrate support to prevent deposition at the edge and backside of the substrate. While shielding is effective in preventing contamination damage, shielding may contribute to other damage, such as poor adhesion and peeling, at the substrate edge during subsequent processing. Shielding the substrate edge also reduces the usable surface area of the substrate.
Therefore, there is a need for a method and apparatus for depositing carbon doped silicon oxide films which improves susceptibility to damage during subsequent processing.
SUMMARY OF THE INVENTION
In one aspect, a process of depositing a carbon doped silicon oxide film having a low dielectric constant (k) on a substrate is provided in which a substrate is positioned in a chamber on a substrate support; a carrier gas, such as an inert gas, is flowed into to the chamber; a process gas mixture is flowed adjacent an edge of the substrate through a purge gas inlet in the substrate support; a plasma is generated, a first carbon silicon gas source is delivered to the chamber, and a carbon doped silicon oxide film is deposited on the substrate.
In another aspect, a film is produce by positioning a substrate in a chamber on a substrate support, flowing a carrier gas into the chamber through a gas inlet, flowing a process gas mixture adjacent an edge of a substrate through a purge gas inlet in the substrate support, generating a plasma, delivering a first carbon silicon gas source to the chamber through a gas inlet, and depositing a film on the substrate having a greater concentration of silicon oxide and a greater hardness around the edge of the substrate than an inner portion of the substrate.
In yet another aspect, a purge heater assembly has a ceramic upper plate and a ceramic lower plate defining a channel therethrough, one or more alignment pin holes disposed in an outside perimeter of the substrate support, an annular purge gas inlet disposed around an outside edge of the upper plate, a shadow ring having one or more alignment pin recesses disposed therein, wherein the upper plate and the shadow ring are machined to form a gap of a predetermined size, and a ceramic shaft having an annular passage therethrough.
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pate
Chen Chen-An
Rocha-Alvarez Juan Carlos
Venkataraman Shankar
Yieh Ellie
Applied Materials Inc.
Meeks Timothy
Moser Patterson & Sheridan
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