Pseudo dual-port DRAM for simultaneous read/write access

Details Pseudo dual-port DRAM for simultaneous read/write access Pseudo dual-port DRAM for simultaneous read/write access

2000-05-22

2001-07-10

Dinh, Son T. (Department: 2751)

Static information storage and retrieval

Read/write circuit

Simultaneous operations

C365S230050, C365S233100

Reexamination Certificate

active

06259634

ABSTRACT:

FIELD OF INVENTION
The invention relates to computer memory, particularly to a dynamic random access memory (DRAM) based system and/or method for simultaneous read/write memory access.
BACKGROUND OF INVENTION
DRAM is often chosen over other faster types of computer memory because a DRAM cell's smaller size allows many more DRAM cells to be packed into a given chip area. In particular, a typical DRAM cell is comprised of a transistor and a capacitor. Thus, a typical DRAM cell is well suited as a building block for constructing memory on increasingly miniaturized silicon chips.
However, DRAM has drawbacks. With slower speed as compared to other types of memory such as a static random access memory (SRAM), DRAM is limited to less time-critical memory applications. As such, in order to offset DRAM's slower speed, dual port is typically implemented for DRAM in order to reduce access time to a DRAM module. Unfortunately, adapting a dual-port DRAM offsets DRAM's compact size advantage. In particular, a dual-port DRAM necessitates twice as many DRAM cells as that of a single-port DRAM. Thus, using a dual-port DRAM entails significant cost (i.e., on the order of two) and circuits design penalty.
Thus, a need exists for “true” random access and simultaneous write and read memory bandwidth without incurring the cost and penalty of a dual-port conventional DRAM.
SUMMARY OF INVENTION
The invention is drawn to a system and/or method for simultaneous read/write access of 1-Transistor (1-T) dynamic random access memory (DRAM). Specifically, in contrast to the prior art approaches, the invention does not rely on a dual-port DRAM to perform both read and write accesses within one single clock cycle. Rather, the invention implements a single-port 1-T DRAM that works in conjunction with a modified design of read sense amplifier (RSA) to perform both read and write accesses effectively within one single clock cycle. As such, the invention retains the compact size that characterize the 1-T DRAM, while allowing high Performance and simultaneous read/write access that characterizes dual-port memory. Hence, the single-port 1-T DRAM of the invention constitutes a pseudo dual-port 1-T DRAM that emulates the dual-port 1-T DRAM's ability in performing simultaneous read/write access of 1-T DRAM.
Preferably, a read access and a write access to a single-port 1-T DRAM are initiated effectively within the same clock cycle. The single-port DRAM is comprised of a pair of cells that share a single local bit line (LBL) to a RSA region comprising a RSA. The RSA region is coupled to a read global bit line (RGBL) and a write global bit line (WGBL). In turn, the RGBL is coupled to the RSA and transfers any read data out from the RSA region, while the WGBL is coupled to the LBL and transfers any write data into the RSA region.
As read access begins in a clock cycle, a first data in one cell (from the pair of cells) is transferred to the RSA via the LBL. Then, upon the first data arriving at the RSA effectively in the same clock cycle, the LBL is isolated from the RSA by shutting off a read pass gate disposed between the LBL and the RSA. In so doing, the LBL is made available for transferring any write data into the single-port 1-T DRAM. In the mean time, still effectively in the same clock cycle, the first data is read out from the RSA via the RGBL.
Effectively in the same clock cycle, as write access begins independent of the read memory access, a second data to be written to another cell (of the pair of cells) is driven onto the WGBL and held therein. The second data is prevented to reach the LBL by a shut-off write pass gate disposed between the LBL and the WGBL. Effectively in the same clock cycle, upon having isolated the LBL from the RSA, the write pass gate is switched on to allow the second data held in the WGBL to enter the LBL, thereby writing the second data into the second cell.


REFERENCES:
patent: 5249165 (1993-09-01), Toda
patent: 5490112 (1996-02-01), Hush et al.
patent: 5726948 (1998-03-01), Hush et al.
patent: 5953285 (1999-09-01), Churchill et al.
patent: 5963497 (1999-10-01), Holland

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