Pseudo differential output buffer, memory chip and memory...

Details Pseudo differential output buffer, memory chip and memory... Pseudo differential output buffer, memory chip and memory...

2005-09-15

2008-11-11

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189110, C326S027000, C327S108000

Reexamination Certificate

active

07450437

ABSTRACT:
An output buffer includes first and second input transistors, first and second output loads and a current source. The first and second input transistors have first current electrodes that are commonly coupled to each other and control electrodes that are respectively coupled to a first differential input signal and a second differential input signal. The first and second output loads are coupled between a first power supply voltage and the first and second input transistors, respectively, wherein an output terminal is coupled to a node where the first output load is coupled to the first input transistor. The current source is coupled between the first current electrodes of the first and second input transistors and a second power supply voltage, wherein the second output load has an impedance value substantially one half of an impedance value of the first output load. Therefore, a differential output signal may be outputted through a single output terminal.

REFERENCES:
patent: 5731711 (1998-03-01), Gabara
patent: 6853213 (2005-02-01), Funaba
patent: 7102905 (2006-09-01), Funaba et al.
patent: 7233201 (2007-06-01), King et al.
patent: 2002/0105360 (2002-08-01), Kim et al.
patent: 07-038403 (1995-02-01), None
patent: 1999-0083148 (1999-11-01), None

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