Programmable scan shift speed control for LBIST

Details Programmable scan shift speed control for LBIST Programmable scan shift speed control for LBIST

2007-09-04

2007-09-04

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

11049522

ABSTRACT:
Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where scan shift operations of the LBIST circuitry are performed at reduced rates. In one embodiment, a base clock signal is gated before being provided to LBIST circuitry. The clock signal is gated to produce an effective clock rate that is reduced in one or more steps from a first rate that is used in a functional phase of LBIST testing to a reduced rate that is used in a scan shift phase. The effective clock rate is stepped back up at the end of the scan shift phase to the first rate which is used in the following functional phase.

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“A methodology for testing high-performance circuits at arbitrarily low test frequency” by Nummer et al. Proceedings of the IEEE VLSI Test Symposium 2001. p. 68-74.

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