Programmable memory cell using charge trapping in a gate oxide

Details Programmable memory cell using charge trapping in a gate oxide Programmable memory cell using charge trapping in a gate oxide

2005-06-21

2005-06-21

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S189011, C365S185280, C365S185230, C365S185180

Reexamination Certificate

active

06909635

ABSTRACT:
An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. According to the teachings of the present invention, the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

REFERENCES:
patent: 3805130 (1974-04-01), Yamazaki
patent: 3992701 (1976-11-01), Abbas et al.
patent: 4051354 (1977-09-01), Choate
patent: 4173766 (1979-11-01), Hayes
patent: 4661833 (1987-04-01), Mizutani
patent: 4761768 (1988-08-01), Turner et al.
patent: 4766569 (1988-08-01), Turner et al.
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 4939559 (1990-07-01), DiMaria et al.
patent: 5172204 (1992-12-01), Hartstein
patent: 5298447 (1994-03-01), Hong
patent: 5324681 (1994-06-01), Lowrey et al.
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5414658 (1995-05-01), Challa
patent: 5493141 (1996-02-01), Ricco et al.
patent: 5544118 (1996-08-01), Harari
patent: 5740104 (1998-04-01), Forbes
patent: 5763912 (1998-06-01), Parat et al.
patent: 5764096 (1998-06-01), Lipp et al.
patent: 5768192 (1998-06-01), Eitan
patent: 5781477 (1998-07-01), Rinerson et al.
patent: 5801401 (1998-09-01), Forbes
patent: 5828099 (1998-10-01), Van Dort et al.
patent: 5851893 (1998-12-01), Gardner et al.
patent: 5852306 (1998-12-01), Forbes
patent: 5867425 (1999-02-01), Wong
patent: 5959896 (1999-09-01), Forbes
patent: 5978273 (1999-11-01), Shigemura
patent: 6031263 (2000-02-01), Forbes et al.
patent: 6038168 (2000-03-01), Allen et al.
patent: 6140181 (2000-10-01), Forbes et al.
patent: 6141248 (2000-10-01), Forbes et al.
patent: 6180957 (2001-01-01), Miyasaka et al.
patent: 6191445 (2001-02-01), Fujiwara
patent: 6229733 (2001-05-01), Male
patent: 6232643 (2001-05-01), Forbes et al.
patent: 6243298 (2001-06-01), Lee et al.
patent: 6246606 (2001-06-01), Forbes et al.
patent: 6249020 (2001-06-01), Forbes et al.
patent: 6272042 (2001-08-01), Kato et al.
patent: 6307775 (2001-10-01), Forbes et al.
patent: 6351411 (2002-02-01), Forbes et al.
patent: 6452835 (2002-09-01), Diorio et al.
patent: 6456535 (2002-09-01), Forbes et al.
patent: 6469352 (2002-10-01), Ohshima et al.
patent: 6504762 (2003-01-01), Harari
patent: 6510086 (2003-01-01), Kato et al.
patent: 6521958 (2003-02-01), Forbes et al.
patent: 6545314 (2003-04-01), Forbes et al.
patent: 6577263 (2003-06-01), Saito
patent: 6614693 (2003-09-01), Lee et al.
patent: 6664601 (2003-12-01), King
patent: 6700821 (2004-03-01), Forbes et al.
patent: 6754108 (2004-06-01), Forbes
patent: 6781876 (2004-08-01), Forbes
patent: 6804136 (2004-10-01), Forbes
patent: 2001/0032997 (2001-10-01), Forbes et al.
patent: 2003/0234420 (2003-12-01), Forbes
patent: 2003/0235075 (2003-12-01), Forbes
patent: 2003/0235076 (2003-12-01), Forbes
patent: 2003/0235077 (2003-12-01), Forbes
patent: 2003/0235079 (2003-12-01), Forbes
patent: 2003/0235081 (2003-12-01), Forbes
patent: 2003/0235085 (2003-12-01), Forbes
patent: 2004/0004245 (2004-01-01), Forbes et al.
patent: 2004/0004247 (2004-01-01), Forbes
patent: 2004/0004859 (2004-01-01), Forbes
patent: 2004/0130951 (2004-07-01), Forbes
patent: 06-283713 (1994-10-01), None
“MT28F002B5 Flash Memory Data Sheet”,Micron Technology, Inc., (Jan. 2000).
Adler, E. , et al., “The Evolution of IBM CMOS DRAM Technology”,IBM Journal of Research&Development, 39(1-2), (Jan.-Mar. 1995),167-188.
Dekeersmaecker, R. , et al., “Electron Trapping and Detrapping Characteristics of Arsenic-Implanted SiO(2) Layers”,J. Appl. Phys., 51, (Feb. 1980),1085-1101.
Dimaria, D. , et al., “Capture and Emission of Electrons at 2.4-eV-Deep Trap Level in SiO(2) Films”,Physical Review B, 11, (Jun. 1975),5023-5030.
Dimaria, D. , et al., “Enhanced Conduction and Minimized Charge Trapping in Electrically Alterable Read-Only Memories Using Off-Stoichiometric Silicon Dioxide Films”,J. Appl. Phys., 55, (Apr. 1984),3000-3019.
Eitan, Boaz , “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”,IEEE Electron Device Letters, 21(11), (Nov. 2000),543-545.
Fischetti, M. V., et al., “The effect of gate metal and SiO2 thickness on the generation of donor states at the Si-SiO2 interface”,Journal of Applied Physics, vol. 57, No. 2, (Jan. 1985),418-424.
Forbes, L. , et al., “Thermal Re-Emission of Trapped Hot Electrons in NMOS Transistors”,IEEE Trans. on Electron Devices, 38, (Dec. 1991),2712.
Hanafi, H. , et al., “Fast and Long Retention-Time Nano-Crystal Memory”,IEEE Trans. on Electron Devices, 43, (Sep. 1996),1553-1558.
Hori, T. , et al., “A MOSFET with Si-Implanted Gate-SiO(2) Insulator for Nonvolatile Memory Applications”,Int'l Electron Devices Meeting: Technical Digest, San Francisco, CA,(Dec. 1992),469-472.
Hsu, C. , et al., “Observation of Threshold Oxide Electric Field for Trap Generation in Oxide Films on Silicon”,J. Appl. Phys., 63, (Jun. 1988),5882-5884.
Huntley, D. , et al., “Deep Traps in Quartz and Their Use for Optical Dating”,Canadian J. Physics, 74, (Mar./Apr. 1996),81-91.
Hwang, N. , et al., “Tunneling and Thermal Emission of Electrons at Room Temperature and Above from a Distribution of Deep Traps in SiO2”,Proc. Int'l Elec. Devices and Materials Symp., Taiwan,(Nov. 1992),559-562.
Kalnitsky, A. , et al., “Memory Effect and Enhanced Conductivity in Si-Implanted Thermally Grown SiO(2)”,IEEE Trans. on Electron Devices, ED-34, (Nov. 1987),2372.
Kalnitsky, A. , et al., “Rechargeable E' Centers in Silicon-Implanted SiO(2) Films”,J. Appl Phys., 67, (Jun. 1990),7359-7367.
Lee, M. , et al., “Thermal Self-Limiting Effects in the Long-Term AC Stress on N-Channel LDD MOSFET's”,Proc.: 9th Biennial University/Government/Industry Microelectronics Symp., Melbourne, FL,(Jun., 1991),93-97.
Lusky, Eli, et al., “Spatial characterization of Channel hot electron injection Utilizing subthreshold slope of NROM memory device”, pp. 1-2.
Miller, A. , “Silicon Dioxide”, MIT, www.a.mit.edu/people/tk/tks/silicon-dioxide.html.
Ning, T. H., “Capture cross section and trap concentration of holes in silicon dioxide”,Journal of Applied Physics, vol. 47, No. 3, (Mar. 1976),1079-1081.
Ning, T. H., et al., “Completely electrically reprogrammable nonvolatile memory device using conventional p-channel MOSFET”,IBM Technical Disclosure Bulletin, vol. 20, No. 5, (Oct. 1977),2016.
Ning, T. H., et al., “Erasable nonvolatile memory device using hole trapping in SiO2”,IBM Technical Disclosure Bulletin, vol. 18, No. 8, (Jan. 1976),2740-2742.
Roizin, Yakov , et al., ““Dummy” GOX for Optimization of microFLASH Technology”, 2 pages.
Roizin, Yakov , et al., “Activation Energy of Traps in the ONO Stack of microFLASH Memory Cells”, 2 pages.
Samanta, Piyas , et al., “Coupled charge trapping dynamics in thin SiO2 gate oxide under Fowler-Nordheim stress at low electron fluence”,Journal of Applied Physics, vol. 83, No. 5, (Mar. 1998),2662-2669.
Takeuchi, K. , et al., “A Double-Level-V Select Gate Array Architecture for Multilevel NANAD Flash Memories”,IEEE Journal of Solid-State Circuits, 31, (Apr. 1996),602-609.
Thomas, J. H., et al., “Electron Trapping Levels in Silicon Dioxide Thermally Grown on Silicon”,J. Physics and Chemistry of Solids, vol. 33, (1972),2197-2216.
Thompson, S. , et al., “Positive Charge Generation in SiO(2) by Electron-Impact Emission of Trapped Electrons”,J. Appl. Phys., 72, (Nov. 1992),4683-4695.
Thompson, S. , et al., “Tunneling and Thermal Emissio

Affiliated with

Also associated with

Rating

Programmable memory cell using charge trapping in a gate oxide does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable memory cell using charge trapping in a gate oxide, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable memory cell using charge trapping in a gate oxide will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3469944