Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-09-12
2002-09-17
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S240000, C714S718000
Reexamination Certificate
active
06452848
ABSTRACT:
BACKGROUND
The present invention relates generally to integrated circuit memory devices and, more particularly, to an apparatus and method for generating desired data test patterns for RAM BIST devices.
As Application Specific Integrated Circuit (ASIC) technologies expand into new markets, the need for denser embedded memory increases. For example, markets in portable and multimedia applications such as cellular phones and personal digital assistants demand increased density of embedded memory for higher function and lower power consumption. In order to accommodate this increased demand, embedded DRAM (eDRAM) macros have been offered in state-of-the-art ASIC portfolios. The integration of eDRAM into ASIC designs has intensified the focus on how best to test a high-density macro, as complex as DRAM, in a logic test environment. The traditional use of Direct Memory Access (DMA) testing, however, proves to be costly in terms of silicon area, available I/O pins, wiring complexity and test time.
Accordingly, a more attractive solution to the embedded-device logic test problem has been through the use of a Built-In Self Test (BIST) system that is adapted to provide all of the elements sufficient to provide high-fault coverage on DRAM. Such elements include, for example, the calculation of a two-dimensional redundancy solution, pattern programming flexibility, at-speed testing, and test mode application for margin testing. The development of BIST capabilities has allowed the testing of large, embedded memories on logic testers without added die area or performance testing inaccuracies associated with isolation multiplexers.
One potential drawback associated with existing BIST systems stems from the fact that the desired data test patterns to be applied to memory array are typically pre-programmed or fixed at the time of the BIST design. Thus, in the event that new data patterns or a greater number of simple data patterns are desired, commands already defined and hard-coded into a microprogram (ROM) within the BIST architecture are then required to be reprogrammed. However, such reprogramming also increases the time and cost involved in memory test applications. Furthermore, for more complex data types, it may be necessary to redesign the BIST itself. This process is even more lengthy as it involves replacement of a portion of the BIST design, resulting in verification of the new design as well as multiple, new production masks.
BRIEF SUMMARY
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a programmable data generator for generating input test data to be applied to a semiconductor memory array. In an exemplary embodiment of the invention, the data generator includes a programmable address scramble register which has a plurality of storage locations associated therewith. The plurality of storage locations corresponds to array address bits associated with an address generator. A first exclusive OR (XOR) logic structure is coupled to the address generator and the address scramble register, wherein the first XOR logic structure generates an address-dependent, data scramble output signal that ultimately determines a data pattern to be applied to the memory array.
In a preferred embodiment, the address-dependent, data scramble output signal is a function of a pre-selected set of the array address bits, wherein the pre-selected array address bits are selected by the values of a series of programmed data bits contained in the address scramble register. In addition, a data word register has a plurality of storage locations associated therewith for containing a programmed data word therein. The data word comprises a portion of the data pattern to be applied to the memory array. A second XOR logic structure has data bits from the data word, along with the address-dependent, data scramble output signal as inputs thereto. The second XOR logic structure thereby generates the data pattern to be applied to the memory array.
Preferably, the first XOR logic structure includes a plurality of AND gates, with each of the plurality of AND gates having one of the data bits in said address scramble register as a first input thereto, and one of the array address bits as a second input thereto. The first XOR logic structure further includes an XOR gate which has as inputs thereto the outputs of the plurality of AND gates, and a data polarity signal. The data polarity signal is indicative of a desired pattern data polarity. Furthermore, the second XOR logic structure preferably includes a plurality of XOR gates, with each of the plurality of XOR gates further having one of the data bits from the data word as a first input thereto, and the address-dependent, data scramble output signal as a second input thereto.
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Dreibelbis Jeffrey H.
Jakobsen Peter O.
Obremski Thomas E.
Cantor & Colburn LLP
Hoang Huan
International Business Machines - Corporation
Walsh Robert
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