Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
1999-08-25
2001-07-17
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230080, C365S185250
Reexamination Certificate
active
06262920
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to latches used in processing systems, and in particular, the present invention relates to program latches in memory devices.
BACKGROUND OF THE INVENTION
Non-volatile memories are extensively used for storing data in processing systems. Examples include erasable programmable read-only memories (EPROM), electrically erasable programmable read-only memories (EEPROM), and Flash memory. These memories are typically internally arranged such that memory cells form arrays consisting of rows and columns. The rows and columns have decode blocks associated therewith, so that any one cell can be uniquely specified.
For programming purposes, non-volatile memories generally have bitlines for carrying data through the array in one dimension. For example, a common technique in memory design is to have bitlines traverse the array in the “Y” direction, such that each cell in a column shares the same bitline during programming. The bitlines are commonly driven during programming by program latches which have been loaded with the desired data prior to programming the memory cells. The number of program latches generally corresponds to the number of columns in the array.
Program latches are generally loaded a subset at a time, with the size of the subset being constrained by the width of the data bus external to the integrated circuit. For example, in a typical device having an 8 bit wide external data bus, but having 256 program latches internal to the device, 32 load operations of 8 bits each are required to load all 256 program latches prior to a programming operation. One well known method of loading a subset of the latches is to provide decoding circuitry that selects the subset to be loaded and de-selects the subset not to be loaded, thereby only asserting control signals corresponding to the set to be loaded. This decoding circuitry consumes space on the integrated circuit.
It is desirable to minimize the size of the program latches in part because when less space is consumed by the latches, more space is available for other circuitry for any given die size. One recognized method of reducing the size of program latches is to do away with the decoding circuitry so that all program latches receive the same “load” signal, and then only driving the input data lines of the data latches to be loaded, and to let the remaining data input lines float. This approach, however, creates a new set of problems, including the problem that the capacitance of the floating data input lines can present a substantial load to the inputs of the latches not intended for loading. If the capacitive load is great enough, charge is “shared” between the capacitive load on the input data line and the input of the latch to the extent that the logic sense of the latch input can be upset, thereby modifying the latch contents in error. This “charge sharing” is undesirable.
For the reasons stated above, and for other reasons stated be low which will become apparent to those skilled in the art up on reading and understanding the present specification, there is a need in the art for a method and apparatus to provide immunity from charge sharing in latch designs.
SUMMARY OF THE INVENTION
The above mentioned problems with charge sharing and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, an integrated circuit is described which includes a latch with a capacitive output load, and a latch bypass path coupled to the input of the latch and to the output of the latch which operates to charge the capacitive load on the output. In another embodiment an integrated circuit is described which includes a plurality of latches responsive to a latch load signal, where each of the of latches includes a storage element and a latch load transistor coupled to the input of the storage element, where each of the latch load transistors is responsive to the same latch load signal.
In yet another embodiment, a memory device having memory cells arranged in columns is described. Each of the cells in a column is connected to a shared bitline having a bitline capacitance. The memory device also includes a plurality of program latches, each having an output coupled to a separate shared bitline. Each program latch in turn includes a storage element and a bypass element coupled between the input and the output of the program latch. A processing system which includes the aforementioned memory device is also described.
A method of operating a latch which has a capacitive input load and a capacitive output load is also described. The method includes coupling a storage element within the latch to the capacitive input load, and coupling the capacitive input load to the capacitive output load. A method of loading a subset of a plurality of latches is also described. Each latch has a capacitive output load, and each is conditionally coupled to a separate data input, which may or may not be driven. The method includes coupling the plurality of latches to their respective data inputs, coupling the capacitive output load of each of the plurality of latches to their respective data inputs, and driving with data the data inputs corresponding to the set of latches to be loaded.
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Bajwa Asim
Louie Benjamin
Elms Richard
Micro)n Technology, Inc.
Nguyen Tuan T.
Schwegman Lundberg Woessner & Kluth P.A.
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